| Message ID | 20250324160617.15379-1-bp@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: x86: Sort CPUID_8000_0021_EAX leaf bits properly | expand |
On Mon, Mar 24, 2025, Borislav Petkov wrote: > From: "Borislav Petkov (AMD)" <bp@alien8.de> > > WRMSR_XX_BASE_NS is bit 1 so put it there, add some new bits as > comments only. > > Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> > --- > arch/x86/kvm/cpuid.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 121edf1f2a79..e98ab18f784b 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -1160,6 +1160,7 @@ void kvm_set_cpu_caps(void) > > kvm_cpu_cap_init(CPUID_8000_0021_EAX, > F(NO_NESTED_DATA_BP), > + F(WRMSR_XX_BASE_NS), > /* > * Synthesize "LFENCE is serializing" into the AMD-defined entry > * in KVM's supported CPUID, i.e. if the feature is reported as > @@ -1173,10 +1174,14 @@ void kvm_set_cpu_caps(void) > SYNTHESIZED_F(LFENCE_RDTSC), > /* SmmPgCfgLock */ > F(NULL_SEL_CLR_BASE), > + /* UpperAddressIgnore */ > F(AUTOIBRS), > EMULATED_F(NO_SMM_CTL_MSR), > + /* FSRS */ > + /* FSRC */ I'm going to skip these, as they aren't yet publicly documented, and there are patches proposed to add actual support. I wouldn't care all that much if these didn't collide with Intel's version (the proposed patches name them AMD_FSxx). https://lore.kernel.org/all/20241204134345.189041-2-davydov-max@yandex-team.ru > /* PrefetchCtlMsr */ > - F(WRMSR_XX_BASE_NS), > + /* GpOnUserCpuid */ > + /* EPSF */ FWIW, this one's also not in the APM (though the only APM I can find is a year old), though it's in tools/x86/kcpuid. > SYNTHESIZED_F(SBPB), > SYNTHESIZED_F(IBPB_BRTYPE), > SYNTHESIZED_F(SRSO_NO), > -- > 2.43.0 >
On Thu, Apr 10, 2025 at 02:46:39PM -0700, Sean Christopherson wrote: > I'm going to skip these, as they aren't yet publicly documented, https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip > and there are patches proposed to add actual support. I wouldn't care all > that much if these didn't collide with Intel's version (the proposed patches > name them AMD_FSxx). > > https://lore.kernel.org/all/20241204134345.189041-2-davydov-max@yandex-team.ru Pff, I think the right thing to do is to detect those and when set, set the Intel flags because they're basically the same. Lemme go reply there. ... goes and replies... > > > /* PrefetchCtlMsr */ > > - F(WRMSR_XX_BASE_NS), > > + /* GpOnUserCpuid */ > > + /* EPSF */ > > FWIW, this one's also not in the APM (though the only APM I can find is a year old), > though it's in tools/x86/kcpuid. See above. Yeah, the PPRs have them earlier than the APM. Thx.
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 121edf1f2a79..e98ab18f784b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1160,6 +1160,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_init(CPUID_8000_0021_EAX, F(NO_NESTED_DATA_BP), + F(WRMSR_XX_BASE_NS), /* * Synthesize "LFENCE is serializing" into the AMD-defined entry * in KVM's supported CPUID, i.e. if the feature is reported as @@ -1173,10 +1174,14 @@ void kvm_set_cpu_caps(void) SYNTHESIZED_F(LFENCE_RDTSC), /* SmmPgCfgLock */ F(NULL_SEL_CLR_BASE), + /* UpperAddressIgnore */ F(AUTOIBRS), EMULATED_F(NO_SMM_CTL_MSR), + /* FSRS */ + /* FSRC */ /* PrefetchCtlMsr */ - F(WRMSR_XX_BASE_NS), + /* GpOnUserCpuid */ + /* EPSF */ SYNTHESIZED_F(SBPB), SYNTHESIZED_F(IBPB_BRTYPE), SYNTHESIZED_F(SRSO_NO),