diff mbox series

[6/6] arm64: dts: qcom: qcm2290: Add CAMSS node

Message ID 20250416120908.206873-6-loic.poulain@oss.qualcomm.com (mailing list archive)
State New
Headers show
Series [1/6] media: qcom: camss: Add support for TFE (Spectra 340) | expand

Commit Message

Loic Poulain April 16, 2025, 12:09 p.m. UTC
Add node for the QCM2290 camera subsystem.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcm2290.dtsi | 93 +++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

Comments

Konrad Dybcio April 16, 2025, 2:46 p.m. UTC | #1
On 4/16/25 2:09 PM, Loic Poulain wrote:
> Add node for the QCM2290 camera subsystem.
> 
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 93 +++++++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> index f0746123e594..4b81e721e50c 100644
> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> @@ -1579,6 +1579,99 @@ adreno_smmu: iommu@59a0000 {
>  			#iommu-cells = <2>;
>  		};
>  
> +		camss: camss@5c52000 {

@5c6e000
(first reg entry)

> +			compatible = "qcom,qcm2290-camss";
> +
> +			reg = <0 0x5c6e000 0 0x1000>,
> +			      <0 0x5c75000 0 0x1000>,
> +			      <0 0x5c52000 0 0x1000>,
> +			      <0 0x5c53000 0 0x1000>,
> +			      <0 0x5c6f000 0 0x4000>,
> +			      <0 0x5c76000 0 0x4000>;
> +			reg-names = "csid0",
> +				    "csid1",
> +				    "csiphy0",
> +				    "csiphy1",
> +				    "vfe0",
> +				    "vfe1";

we also have a pair of TPGs at 0x5c6[68]000 - I think it would be good to
describe them from the get-go

> +
> +			interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;

the two TPGs would have IRQs 309 and 310

[...]

> +			interconnects = <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
> +					 &config_noc SLAVE_CAMERA_CFG RPM_ALWAYS_TAG>,

This one should get a RPM_ACTIVE_TAG instead, on both endpoints

Konrad
Loic Poulain April 16, 2025, 3:01 p.m. UTC | #2
On Wed, Apr 16, 2025 at 4:46 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/16/25 2:09 PM, Loic Poulain wrote:
> > Add node for the QCM2290 camera subsystem.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 93 +++++++++++++++++++++++++++
> >  1 file changed, 93 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > index f0746123e594..4b81e721e50c 100644
> > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > @@ -1579,6 +1579,99 @@ adreno_smmu: iommu@59a0000 {
> >                       #iommu-cells = <2>;
> >               };
> >
> > +             camss: camss@5c52000 {
>
> @5c6e000
> (first reg entry)

Ah right, I reordered reg to be aligned with other camss drivers.
Should I keep that order (and update node name) or reorder with phy
lower addresses first (PHYs)?

>
> > +                     compatible = "qcom,qcm2290-camss";
> > +
> > +                     reg = <0 0x5c6e000 0 0x1000>,
> > +                           <0 0x5c75000 0 0x1000>,
> > +                           <0 0x5c52000 0 0x1000>,
> > +                           <0 0x5c53000 0 0x1000>,
> > +                           <0 0x5c6f000 0 0x4000>,
> > +                           <0 0x5c76000 0 0x4000>;
> > +                     reg-names = "csid0",
> > +                                 "csid1",
> > +                                 "csiphy0",
> > +                                 "csiphy1",
> > +                                 "vfe0",
> > +                                 "vfe1";
>
> we also have a pair of TPGs at 0x5c6[68]000 - I think it would be good to
> describe them from the get-go

Indeed, will do.

>
> > +
> > +                     interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> > +                                  <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
>
> the two TPGs would have IRQs 309 and 310
>
> [...]
>
> > +                     interconnects = <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
> > +                                      &config_noc SLAVE_CAMERA_CFG RPM_ALWAYS_TAG>,
>
> This one should get a RPM_ACTIVE_TAG instead, on both endpoints

ok, thanks.
Konrad Dybcio April 16, 2025, 3:02 p.m. UTC | #3
On 4/16/25 5:01 PM, Loic Poulain wrote:
> On Wed, Apr 16, 2025 at 4:46 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 4/16/25 2:09 PM, Loic Poulain wrote:
>>> Add node for the QCM2290 camera subsystem.
>>>
>>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 93 +++++++++++++++++++++++++++
>>>  1 file changed, 93 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> index f0746123e594..4b81e721e50c 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> @@ -1579,6 +1579,99 @@ adreno_smmu: iommu@59a0000 {
>>>                       #iommu-cells = <2>;
>>>               };
>>>
>>> +             camss: camss@5c52000 {
>>
>> @5c6e000
>> (first reg entry)
> 
> Ah right, I reordered reg to be aligned with other camss drivers.
> Should I keep that order (and update node name) or reorder with phy
> lower addresses first (PHYs)?

That seems to be wildly different across a number of socs, so let's
just say this is okay as is, as we're not gonna find any reasonable
order in here

Konrad
Bryan O'Donoghue April 16, 2025, 3:03 p.m. UTC | #4
On 16/04/2025 16:01, Loic Poulain wrote:
>> @5c6e000
>> (first reg entry)
> Ah right, I reordered reg to be aligned with other camss drivers.
> Should I keep that order (and update node name) or reorder with phy
> lower addresses first (PHYs)?
> 
>>> +                     compatible = "qcom,qcm2290-camss";
>>> +
>>> +                     reg = <0 0x5c6e000 0 0x1000>,
>>> +                           <0 0x5c75000 0 0x1000>,
>>> +                           <0 0x5c52000 0 0x1000>,
>>> +                           <0 0x5c53000 0 0x1000>,
>>> +                           <0 0x5c6f000 0 0x4000>,
>>> +                           <0 0x5c76000 0 0x4000>;
>>> +                     reg-names = "csid0",
>>> +                                 "csid1",
>>> +                                 "csiphy0",
>>> +                                 "csiphy1",
>>> +                                 "vfe0",
>>> +                                 "vfe1";

Please keep consistent with the last committed yaml for CAMSS.

---
bod
Bryan O'Donoghue April 16, 2025, 3:04 p.m. UTC | #5
On 16/04/2025 16:02, Konrad Dybcio wrote:
>>> @5c6e000
>>> (first reg entry)
>> Ah right, I reordered reg to be aligned with other camss drivers.
>> Should I keep that order (and update node name) or reorder with phy
>> lower addresses first (PHYs)?
> That seems to be wildly different across a number of socs, so let's
> just say this is okay as is, as we're not gonna find any reasonable
> order in here

eek no please - we've been trying to make this consistent.

Please do as was done with sm8550. My stress levels can't take another 
change.

---
bod
Loic Poulain April 16, 2025, 4:16 p.m. UTC | #6
On Wed, Apr 16, 2025 at 4:46 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 4/16/25 2:09 PM, Loic Poulain wrote:
> > Add node for the QCM2290 camera subsystem.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/qcm2290.dtsi | 93 +++++++++++++++++++++++++++
> >  1 file changed, 93 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > index f0746123e594..4b81e721e50c 100644
> > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
> > @@ -1579,6 +1579,99 @@ adreno_smmu: iommu@59a0000 {
> >                       #iommu-cells = <2>;
> >               };
> >
> > +             camss: camss@5c52000 {
>
> @5c6e000
> (first reg entry)
>
> > +                     compatible = "qcom,qcm2290-camss";
> > +
> > +                     reg = <0 0x5c6e000 0 0x1000>,
> > +                           <0 0x5c75000 0 0x1000>,
> > +                           <0 0x5c52000 0 0x1000>,
> > +                           <0 0x5c53000 0 0x1000>,
> > +                           <0 0x5c6f000 0 0x4000>,
> > +                           <0 0x5c76000 0 0x4000>;
> > +                     reg-names = "csid0",
> > +                                 "csid1",
> > +                                 "csiphy0",
> > +                                 "csiphy1",
> > +                                 "vfe0",
> > +                                 "vfe1";
>
> we also have a pair of TPGs at 0x5c6[68]000 - I think it would be good to
> describe them from the get-go

If we want to be ready for TPG, we may also want a camss 'top' reg
(0x05C11000), since it seems to be required for configuring CSID input
mux (TPG vs CSIPHY).
Bryan O'Donoghue April 16, 2025, 11:38 p.m. UTC | #7
On 16/04/2025 17:16, Loic Poulain wrote:
>> we also have a pair of TPGs at 0x5c6[68]000 - I think it would be good to
>> describe them from the get-go
> If we want to be ready for TPG, we may also want a camss 'top' reg
> (0x05C11000), since it seems to be required for configuring CSID input
> mux (TPG vs CSIPHY).

There's no harm in including the TPG in the reg list.

---
bod
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index f0746123e594..4b81e721e50c 100644
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -1579,6 +1579,99 @@  adreno_smmu: iommu@59a0000 {
 			#iommu-cells = <2>;
 		};
 
+		camss: camss@5c52000 {
+			compatible = "qcom,qcm2290-camss";
+
+			reg = <0 0x5c6e000 0 0x1000>,
+			      <0 0x5c75000 0 0x1000>,
+			      <0 0x5c52000 0 0x1000>,
+			      <0 0x5c53000 0 0x1000>,
+			      <0 0x5c6f000 0 0x4000>,
+			      <0 0x5c76000 0 0x4000>;
+			reg-names = "csid0",
+				    "csid1",
+				    "csiphy0",
+				    "csiphy1",
+				    "vfe0",
+				    "vfe1";
+
+			interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "csid0",
+					  "csid1",
+					  "csiphy0",
+					  "csiphy1",
+					  "vfe0",
+					  "vfe1";
+
+			power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&gcc GCC_CAMSS_AXI_CLK>,
+				 <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+				 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+				 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+				 <&gcc GCC_CAMSS_CPHY_0_CLK>,
+				 <&gcc GCC_CAMSS_CPHY_1_CLK>,
+				 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+				 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+				 <&gcc GCC_CAMSS_TFE_0_CLK>,
+				 <&gcc GCC_CAMSS_TFE_1_CLK>,
+				 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+				 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+				 <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+				 <&gcc GCC_CAMSS_RT_AXI_CLK>;
+			clock-names = "ahb",
+				      "axi",
+				      "top_ahb",
+				      "csi0",
+				      "csi1",
+				      "csiphy0",
+				      "csiphy1",
+				      "csiphy0_timer",
+				      "csiphy1_timer",
+				      "vfe0",
+				      "vfe1",
+				      "vfe0_cphy_rx",
+				      "vfe1_cphy_rx",
+				      "camnoc_nrt_axi",
+				      "camnoc_rt_axi";
+
+			iommus = <&apps_smmu 0x400 0x0>,
+				 <&apps_smmu 0x800 0x0>,
+				 <&apps_smmu 0x820 0x0>,
+				 <&apps_smmu 0x840 0x0>;
+
+			interconnects = <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+					 &config_noc SLAVE_CAMERA_CFG RPM_ALWAYS_TAG>,
+					<&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
+					 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+					<&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
+					 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+			interconnect-names = "ahb",
+					     "hf_mnoc",
+					     "sf_mnoc";
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		mdss: display-subsystem@5e00000 {
 			compatible = "qcom,qcm2290-mdss";
 			reg = <0x0 0x05e00000 0x0 0x1000>;