| Message ID | 20250417112012.785420-1-Wojciech.Dubowik@mt.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: imx8mm-verdin: Link reg_nvcc_sd to usdhc2 | expand |
Hello Wojciech, thanks very much for your patch. On Thu, Apr 17, 2025 at 01:20:11PM +0200, Wojciech Dubowik wrote: > Link LDO5 labeled reg_nvcc_sd from PMIC to align with > hardware configuration specified in the datasheet. > > Without this definition LDO5 will be powered down, disabling > SD card after bootup. This has been introduced in commit > f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5). > > Fixes: f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5) > Cc: stable@vger.kernel.org > > Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com> > --- > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > index 7251ad3a0017..6307c5caf3bc 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > @@ -785,6 +785,7 @@ &usdhc2 { > pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; > pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; > vmmc-supply = <®_usdhc2_vmmc>; > + vqmmc-supply = <®_nvcc_sd>; I am worried just doing this will have some side effects. Before this patch, the switch between 1v8 and 3v3 was done because we have a GPIO, connected to the PMIC, controlled by the USDHC2 instance (MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT, see pinctrl_usdhc2). With your change both the PMIC will be programmed with a different voltage over i2c and the GPIO will also toggle. It does not sound like what we want to do. Maybe we should have a "regulator-gpio" with vin-supply = <®_nvcc_sd>, as we recently did here https://lore.kernel.org/all/20250414123827.428339-1-ivitro@gmail.com/T/#m2964f1126a6732a66a6e704812f2b786e8237354 ? Francesco
> From: Francesco Dolcini <francesco@dolcini.it> > Sent: Thursday, 17 April 2025 15:03 > To: Dubowik Wojciech LCPF-CH <Wojciech.Dubowik@mt.com> > Cc: linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer <s.hauer@pengutronix.de>; Pengutronix Kernel Team > <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; devicetree@vger.kernel.org <devicetree@vger.kernel.org>; imx@lists.linux.dev <imx@lists.linux.dev>; linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>; stable@vger.kernel.org <stable@vger.kernel.org> > Subject: Re: EXTERNAL - [PATCH] arm64: dts: imx8mm-verdin: Link reg_nvcc_sd to usdhc2 > Hello Wojciech, > thanks very much for your patch. > On Thu, Apr 17, 2025 at 01:20:11PM +0200, Wojciech Dubowik wrote: >> Link LDO5 labeled reg_nvcc_sd from PMIC to align with >> hardware configuration specified in the datasheet. >> >> Without this definition LDO5 will be powered down, disabling >> SD card after bootup. This has been introduced in commit >> f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5). >> >> Fixes: f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5) >> Cc: stable@vger.kernel.org >> >> Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com> >> --- >> arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi >> index 7251ad3a0017..6307c5caf3bc 100644 >> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi >> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi >> @@ -785,6 +785,7 @@ &usdhc2 { >> pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; >> pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; >> vmmc-supply = <®_usdhc2_vmmc>; >> + vqmmc-supply = <®_nvcc_sd>; > >I am worried just doing this will have some side effects. > >Before this patch, the switch between 1v8 and 3v3 was done because we >have a GPIO, connected to the PMIC, controlled by the USDHC2 instance >(MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT, see pinctrl_usdhc2). > >With your change both the PMIC will be programmed with a different >voltage over i2c and the GPIO will also toggle. It does not sound like >what we want to do. > >Maybe we should have a "regulator-gpio" with vin-supply = ><®_nvcc_sd>, as we recently did here >https://lore.kernel.org/all/20250414123827.428339-1-ivitro@gmail.com/T/#m2964f1126a6732a66a6e704812f2b786e8237354 >? >Francesco I will have a look at your suggestion and try to test them on verdin. I won't have access to HW over Eastern so the patch will have to wait. Wojtek
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7251ad3a0017..6307c5caf3bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -785,6 +785,7 @@ &usdhc2 { pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd>; }; &wdog1 {
Link LDO5 labeled reg_nvcc_sd from PMIC to align with hardware configuration specified in the datasheet. Without this definition LDO5 will be powered down, disabling SD card after bootup. This has been introduced in commit f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5). Fixes: f5aab0438ef1 (regulator: pca9450: Fix enable register for LDO5) Cc: stable@vger.kernel.org Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@mt.com> --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 1 + 1 file changed, 1 insertion(+)