diff mbox

[RFCv3,1/8] v4l2 core: add the missing pieces to support DVI/HDMI/DisplayPort.

Message ID bf682233fde61ca77ed4512ba77271f6daeedb31.1344592468.git.hans.verkuil@cisco.com (mailing list archive)
State New, archived
Headers show

Commit Message

Hans Verkuil Aug. 10, 2012, 11:21 a.m. UTC
These new controls and two new ioctls make it possible to properly support
VGA, DVI-A/D/I, HDMI and DisplayPort connectors. All these controls and the
ioctls are all at the sub-device level. They are meant for V4L2 bridge/platform
drivers or to be accessed on embedded systems through /dev/v4l-subdev* device
nodes.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
---
 include/linux/v4l2-subdev.h |   10 ++++++++++
 include/linux/videodev2.h   |   23 +++++++++++++++++++++++
 2 files changed, 33 insertions(+)

Comments

Soby Mathew Aug. 13, 2012, 11:48 a.m. UTC | #1
Hi Hans,
   The patch seems to cover most of the requirement.  I find 2 gaps:

> +/*  DV-class control IDs defined by V4L2 */
> +#define V4L2_CID_DV_CLASS_BASE                 (V4L2_CTRL_CLASS_DV | 0x900)
> +#define V4L2_CID_DV_CLASS                      (V4L2_CTRL_CLASS_DV | 1)
> +
> +#define        V4L2_CID_DV_TX_HOTPLUG                  (V4L2_CID_DV_CLASS_BASE + 1)
> +#define        V4L2_CID_DV_TX_RXSENSE                  (V4L2_CID_DV_CLASS_BASE + 2)
> +#define        V4L2_CID_DV_TX_EDID_PRESENT             (V4L2_CID_DV_CLASS_BASE + 3)
> +#define        V4L2_CID_DV_TX_MODE                     (V4L2_CID_DV_CLASS_BASE + 4)
> +enum v4l2_dv_tx_mode {
> +       V4L2_DV_TX_MODE_DVI_D   = 0,
> +       V4L2_DV_TX_MODE_HDMI    = 1,
> +};


Even at the receiver side the DVI/HDMI mode need to be detected. So
probably a control for the RX mode is needed.


> +#define V4L2_CID_DV_TX_RGB_RANGE               (V4L2_CID_DV_CLASS_BASE + 5)
> +enum v4l2_dv_rgb_range {
> +       V4L2_DV_RGB_RANGE_AUTO    = 0,
> +       V4L2_DV_RGB_RANGE_LIMITED = 1,
> +       V4L2_DV_RGB_RANGE_FULL    = 2,
> +};
> +
> +#define        V4L2_CID_DV_RX_POWER_PRESENT            (V4L2_CID_DV_CLASS_BASE + 100)
> +#define V4L2_CID_DV_RX_RGB_RANGE               (V4L2_CID_DV_CLASS_BASE + 101)
> +

Similarly, some sources can support YC mode of transmission instaed of
RGB. To control the YC Quantization Range, we can define  control
V4L2_CID_DV_TX_YC_RANGE

Similar control would be needed at the Rx side also like
V4L2_CID_DV_RX_YC_RANGE.


Best Regards
Soby Mathew
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Hans Verkuil Aug. 13, 2012, 12:15 p.m. UTC | #2
On Mon August 13 2012 13:48:28 Soby Mathew wrote:
> Hi Hans,
>    The patch seems to cover most of the requirement.  I find 2 gaps:
> 
> > +/*  DV-class control IDs defined by V4L2 */
> > +#define V4L2_CID_DV_CLASS_BASE                 (V4L2_CTRL_CLASS_DV | 0x900)
> > +#define V4L2_CID_DV_CLASS                      (V4L2_CTRL_CLASS_DV | 1)
> > +
> > +#define        V4L2_CID_DV_TX_HOTPLUG                  (V4L2_CID_DV_CLASS_BASE + 1)
> > +#define        V4L2_CID_DV_TX_RXSENSE                  (V4L2_CID_DV_CLASS_BASE + 2)
> > +#define        V4L2_CID_DV_TX_EDID_PRESENT             (V4L2_CID_DV_CLASS_BASE + 3)
> > +#define        V4L2_CID_DV_TX_MODE                     (V4L2_CID_DV_CLASS_BASE + 4)
> > +enum v4l2_dv_tx_mode {
> > +       V4L2_DV_TX_MODE_DVI_D   = 0,
> > +       V4L2_DV_TX_MODE_HDMI    = 1,
> > +};
> 
> 
> Even at the receiver side the DVI/HDMI mode need to be detected. So
> probably a control for the RX mode is needed.

We left that part out for the moment: we (Cisco) do not need that at the
moment, and for this first version I wanted to concentrate only on those
parts that were absolutely necessary.

Once it's merged it is much easier to add additional functionality like
that.

> 
> 
> > +#define V4L2_CID_DV_TX_RGB_RANGE               (V4L2_CID_DV_CLASS_BASE + 5)
> > +enum v4l2_dv_rgb_range {
> > +       V4L2_DV_RGB_RANGE_AUTO    = 0,
> > +       V4L2_DV_RGB_RANGE_LIMITED = 1,
> > +       V4L2_DV_RGB_RANGE_FULL    = 2,
> > +};
> > +
> > +#define        V4L2_CID_DV_RX_POWER_PRESENT            (V4L2_CID_DV_CLASS_BASE + 100)
> > +#define V4L2_CID_DV_RX_RGB_RANGE               (V4L2_CID_DV_CLASS_BASE + 101)
> > +
> 
> Similarly, some sources can support YC mode of transmission instaed of
> RGB. To control the YC Quantization Range, we can define  control
> V4L2_CID_DV_TX_YC_RANGE
> 
> Similar control would be needed at the Rx side also like
> V4L2_CID_DV_RX_YC_RANGE.

The question is if you actually need this control for the YC range. For RGB
it is necessary because you cannot rely on the autodetect: too many devices
do not handle that correctly, so you have to be able to override.

For YC the situation seems to be much better and we (Cisco) haven't seen the
need yet to be able to override the automatic YC range setup.

If there is a clear situation where this is necessary, then it can be added.

Regards,

	Hans
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diff mbox

Patch

diff --git a/include/linux/v4l2-subdev.h b/include/linux/v4l2-subdev.h
index 8c57ee9..a426a78 100644
--- a/include/linux/v4l2-subdev.h
+++ b/include/linux/v4l2-subdev.h
@@ -148,6 +148,14 @@  struct v4l2_subdev_selection {
 	__u32 reserved[8];
 };
 
+struct v4l2_subdev_edid {
+	__u32 pad;
+	__u32 start_block;
+	__u32 blocks;
+	__u32 reserved[5];
+	__u8 __user *edid;
+};
+
 #define VIDIOC_SUBDEV_G_FMT	_IOWR('V',  4, struct v4l2_subdev_format)
 #define VIDIOC_SUBDEV_S_FMT	_IOWR('V',  5, struct v4l2_subdev_format)
 #define VIDIOC_SUBDEV_G_FRAME_INTERVAL \
@@ -166,5 +174,7 @@  struct v4l2_subdev_selection {
 	_IOWR('V', 61, struct v4l2_subdev_selection)
 #define VIDIOC_SUBDEV_S_SELECTION \
 	_IOWR('V', 62, struct v4l2_subdev_selection)
+#define VIDIOC_SUBDEV_G_EDID	_IOWR('V', 63, struct v4l2_subdev_edid)
+#define VIDIOC_SUBDEV_S_EDID	_IOWR('V', 64, struct v4l2_subdev_edid)
 
 #endif
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 7a147c8..91939a7 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -1250,6 +1250,7 @@  struct v4l2_ext_controls {
 #define V4L2_CTRL_CLASS_JPEG 0x009d0000		/* JPEG-compression controls */
 #define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000	/* Image source controls */
 #define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000	/* Image processing controls */
+#define V4L2_CTRL_CLASS_DV 0x00a00000		/* Digital Video controls */
 
 #define V4L2_CTRL_ID_MASK      	  (0x0fffffff)
 #define V4L2_CTRL_ID2CLASS(id)    ((id) & 0x0fff0000UL)
@@ -1993,6 +1994,28 @@  enum v4l2_jpeg_chroma_subsampling {
 #define V4L2_CID_LINK_FREQ			(V4L2_CID_IMAGE_PROC_CLASS_BASE + 1)
 #define V4L2_CID_PIXEL_RATE			(V4L2_CID_IMAGE_PROC_CLASS_BASE + 2)
 
+/*  DV-class control IDs defined by V4L2 */
+#define V4L2_CID_DV_CLASS_BASE			(V4L2_CTRL_CLASS_DV | 0x900)
+#define V4L2_CID_DV_CLASS			(V4L2_CTRL_CLASS_DV | 1)
+
+#define	V4L2_CID_DV_TX_HOTPLUG			(V4L2_CID_DV_CLASS_BASE + 1)
+#define	V4L2_CID_DV_TX_RXSENSE			(V4L2_CID_DV_CLASS_BASE + 2)
+#define	V4L2_CID_DV_TX_EDID_PRESENT		(V4L2_CID_DV_CLASS_BASE + 3)
+#define	V4L2_CID_DV_TX_MODE			(V4L2_CID_DV_CLASS_BASE + 4)
+enum v4l2_dv_tx_mode {
+	V4L2_DV_TX_MODE_DVI_D	= 0,
+	V4L2_DV_TX_MODE_HDMI	= 1,
+};
+#define V4L2_CID_DV_TX_RGB_RANGE		(V4L2_CID_DV_CLASS_BASE + 5)
+enum v4l2_dv_rgb_range {
+	V4L2_DV_RGB_RANGE_AUTO	  = 0,
+	V4L2_DV_RGB_RANGE_LIMITED = 1,
+	V4L2_DV_RGB_RANGE_FULL	  = 2,
+};
+
+#define	V4L2_CID_DV_RX_POWER_PRESENT		(V4L2_CID_DV_CLASS_BASE + 100)
+#define V4L2_CID_DV_RX_RGB_RANGE		(V4L2_CID_DV_CLASS_BASE + 101)
+
 /*
  *	T U N I N G
  */