| Message ID | 1344948061-9436-1-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 14 Aug 2012, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Daniel Vetter <daniel.vetter@ffwll.ch> > > They've changed it ... for no apparent reason. Meh. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/char/agp/intel-agp.h | 1 + > drivers/char/agp/intel-gtt.c | 107 ++++++++++++++++++++++++------------ > drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 4 files changed, 77 insertions(+), 37 deletions(-) > > Applies to -fixes. > > diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h > index 6f007b6..6ec0fff 100644 > --- a/drivers/char/agp/intel-agp.h > +++ b/drivers/char/agp/intel-agp.h > @@ -64,6 +64,7 @@ > #define I830_PTE_SYSTEM_CACHED 0x00000006 > /* GT PTE cache control fields */ > #define GEN6_PTE_UNCACHED 0x00000002 > +#define HSW_PTE_UNCACHED 0x00000000 > #define GEN6_PTE_LLC 0x00000004 > #define GEN6_PTE_LLC_MLC 0x00000006 > #define GEN6_PTE_GFDT 0x00000008 > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c > index 08fc5cb..8f956db 100644 > --- a/drivers/char/agp/intel-gtt.c > +++ b/drivers/char/agp/intel-gtt.c > @@ -44,6 +44,7 @@ struct intel_gtt_driver { > unsigned int is_g33 : 1; > unsigned int is_pineview : 1; > unsigned int is_ironlake : 1; > + unsigned int is_hsw : 1; This bit is set in haswell_gtt_driver, but it's not referenced anywhere, is it? Why do you add it? Am I missing something? BR, Jani. > unsigned int has_pgtbl_enable : 1; > unsigned int dma_mask_size : 8; > /* Chipset specific GTT setup */ > @@ -1156,6 +1157,30 @@ static bool gen6_check_flags(unsigned int flags) > return true; > } > > +static void haswell_write_entry(dma_addr_t addr, unsigned int entry, > + unsigned int flags) > +{ > + unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; > + unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; > + u32 pte_flags; > + > + if (type_mask == AGP_USER_MEMORY) > + pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID; > + else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { > + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; > + if (gfdt) > + pte_flags |= GEN6_PTE_GFDT; > + } else { /* set 'normal'/'cached' to LLC by default */ > + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; > + if (gfdt) > + pte_flags |= GEN6_PTE_GFDT; > + } > + > + /* gen6 has bit11-4 for physical addr bit39-32 */ > + addr |= (addr >> 28) & 0xff0; > + writel(addr | pte_flags, intel_private.gtt + entry); > +} > + > static void gen6_write_entry(dma_addr_t addr, unsigned int entry, > unsigned int flags) > { > @@ -1382,6 +1407,16 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { > .check_flags = gen6_check_flags, > .chipset_flush = i9xx_chipset_flush, > }; > +static const struct intel_gtt_driver haswell_gtt_driver = { > + .gen = 6, > + .setup = i9xx_setup, > + .cleanup = gen6_cleanup, > + .write_entry = haswell_write_entry, > + .dma_mask_size = 40, > + .is_hsw = 1, > + .check_flags = gen6_check_flags, > + .chipset_flush = i9xx_chipset_flush, > +}; > static const struct intel_gtt_driver valleyview_gtt_driver = { > .gen = 7, > .setup = i9xx_setup, > @@ -1499,77 +1534,77 @@ static const struct intel_gtt_driver_description { > { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, > "ValleyView", &valleyview_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG, > - "Haswell", &sandybridge_gtt_driver }, > + "Haswell", &haswell_gtt_driver }, > { 0, NULL, NULL } > }; > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 4584f7f..9e4e0b4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -261,7 +261,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, > pte_flags |= GEN6_PTE_CACHE_LLC; > break; > case I915_CACHE_NONE: > - pte_flags |= GEN6_PTE_UNCACHED; > + if (IS_HASWELL(dev)) > + pte_flags |= HSW_PTE_UNCACHED; > + else > + pte_flags |= GEN6_PTE_UNCACHED; > break; > default: > BUG(); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 321ae72..ab8cffe 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -115,6 +115,7 @@ > > #define GEN6_PTE_VALID (1 << 0) > #define GEN6_PTE_UNCACHED (1 << 1) > +#define HSW_PTE_UNCACHED (0) > #define GEN6_PTE_CACHE_LLC (2 << 1) > #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) > #define GEN6_PTE_CACHE_BITS (3 << 1) > -- > 1.7.11.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Paulo Zanoni <przanoni@gmail.com> writes:
> +#define HSW_PTE_UNCACHED 0x00000000
Are you sure this value should be zero? It seems pretty unlikely to me.
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 6f007b6..6ec0fff 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -64,6 +64,7 @@ #define I830_PTE_SYSTEM_CACHED 0x00000006 /* GT PTE cache control fields */ #define GEN6_PTE_UNCACHED 0x00000002 +#define HSW_PTE_UNCACHED 0x00000000 #define GEN6_PTE_LLC 0x00000004 #define GEN6_PTE_LLC_MLC 0x00000006 #define GEN6_PTE_GFDT 0x00000008 diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 08fc5cb..8f956db 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -44,6 +44,7 @@ struct intel_gtt_driver { unsigned int is_g33 : 1; unsigned int is_pineview : 1; unsigned int is_ironlake : 1; + unsigned int is_hsw : 1; unsigned int has_pgtbl_enable : 1; unsigned int dma_mask_size : 8; /* Chipset specific GTT setup */ @@ -1156,6 +1157,30 @@ static bool gen6_check_flags(unsigned int flags) return true; } +static void haswell_write_entry(dma_addr_t addr, unsigned int entry, + unsigned int flags) +{ + unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; + unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; + u32 pte_flags; + + if (type_mask == AGP_USER_MEMORY) + pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID; + else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; + if (gfdt) + pte_flags |= GEN6_PTE_GFDT; + } else { /* set 'normal'/'cached' to LLC by default */ + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; + if (gfdt) + pte_flags |= GEN6_PTE_GFDT; + } + + /* gen6 has bit11-4 for physical addr bit39-32 */ + addr |= (addr >> 28) & 0xff0; + writel(addr | pte_flags, intel_private.gtt + entry); +} + static void gen6_write_entry(dma_addr_t addr, unsigned int entry, unsigned int flags) { @@ -1382,6 +1407,16 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = { .check_flags = gen6_check_flags, .chipset_flush = i9xx_chipset_flush, }; +static const struct intel_gtt_driver haswell_gtt_driver = { + .gen = 6, + .setup = i9xx_setup, + .cleanup = gen6_cleanup, + .write_entry = haswell_write_entry, + .dma_mask_size = 40, + .is_hsw = 1, + .check_flags = gen6_check_flags, + .chipset_flush = i9xx_chipset_flush, +}; static const struct intel_gtt_driver valleyview_gtt_driver = { .gen = 7, .setup = i9xx_setup, @@ -1499,77 +1534,77 @@ static const struct intel_gtt_driver_description { { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, "ValleyView", &valleyview_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG, - "Haswell", &sandybridge_gtt_driver }, + "Haswell", &haswell_gtt_driver }, { 0, NULL, NULL } }; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4584f7f..9e4e0b4 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -261,7 +261,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, pte_flags |= GEN6_PTE_CACHE_LLC; break; case I915_CACHE_NONE: - pte_flags |= GEN6_PTE_UNCACHED; + if (IS_HASWELL(dev)) + pte_flags |= HSW_PTE_UNCACHED; + else + pte_flags |= GEN6_PTE_UNCACHED; break; default: BUG(); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 321ae72..ab8cffe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -115,6 +115,7 @@ #define GEN6_PTE_VALID (1 << 0) #define GEN6_PTE_UNCACHED (1 << 1) +#define HSW_PTE_UNCACHED (0) #define GEN6_PTE_CACHE_LLC (2 << 1) #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) #define GEN6_PTE_CACHE_BITS (3 << 1)