| Message ID | 1344691906-15985-3-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Aug 11, 2012 at 3:31 PM, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote: > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> FWIW: Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
Hi, On Sat, Aug 11, 2012 at 03:31:43PM +0200, Thomas Petazzoni wrote: > +- gpio-controller: marks the device node as a gpio controller > + > +- ngpios: number of GPIOs this controller has > + > +- #gpio-cells: Should be one. It is the pin number. Most platforms will hit a need to encode polarity of the GPIO, in particular on inputs. Having an extra cell for flags is quite useful.
On Mon, Aug 27, 2012 at 11:53 PM, Olof Johansson <olof@lixom.net> wrote: > Hi, > > On Sat, Aug 11, 2012 at 03:31:43PM +0200, Thomas Petazzoni wrote: >> +- gpio-controller: marks the device node as a gpio controller >> + >> +- ngpios: number of GPIOs this controller has >> + >> +- #gpio-cells: Should be one. It is the pin number. > > Most platforms will hit a need to encode polarity of the GPIO, in > particular on inputs. Having an extra cell for flags is quite useful. Isn't that surplus in this case since this driver has a proper pinctrl backend controlling such stuff? I don't really like pinctrl portions of GPIOs being showeled into the GPIO actually. Or am I just getting this wrong...? Yours, Linus Walleij
On Sun, Sep 2, 2012 at 12:33 AM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Mon, Aug 27, 2012 at 11:53 PM, Olof Johansson <olof@lixom.net> wrote: >> Hi, >> >> On Sat, Aug 11, 2012 at 03:31:43PM +0200, Thomas Petazzoni wrote: >>> +- gpio-controller: marks the device node as a gpio controller >>> + >>> +- ngpios: number of GPIOs this controller has >>> + >>> +- #gpio-cells: Should be one. It is the pin number. >> >> Most platforms will hit a need to encode polarity of the GPIO, in >> particular on inputs. Having an extra cell for flags is quite useful. > > Isn't that surplus in this case since this driver has a proper > pinctrl backend controlling such stuff? I don't really like > pinctrl portions of GPIOs being showeled into the GPIO > actually. Or am I just getting this wrong...? Ah, yes, true. Last time I had to add this was for a platform that lacked pinctrl bindings (exynos). I guess it doesn't hurt to add the flag since it might be used on other OSes that have a gpio driver but not a pinctrl one, but that's a pretty far corner case, no need to revise for it. -Olof
On Wed, Sep 5, 2012 at 6:51 AM, Olof Johansson <olof@lixom.net> wrote: > I guess it doesn't hurt to add the flag since it might be used on > other OSes that have a gpio driver but not a pinctrl one, but that's a > pretty far corner case, no need to revise for it. Sounds a bit ambigous and redundant, as we are in the driver seat for device tree I'd prefer to force every other OS to get their pinctrl concepts right ;-) Linus Walleij
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt new file mode 100644 index 0000000..298436c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -0,0 +1,44 @@ +* Marvell EBU GPIO controller + +Required properties: + +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio" + or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for + Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada + 370. "marvell,mv78200-gpio" should be used for the Discovery + MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP + SoCs (MV78230, MV78260, MV78460). + +- reg: Address and length of the register set for the device. Only one + entry is expected, except for the "marvell,armadaxp-gpio" variant + for which two entries are expected: one for the general registers, + one for the per-cpu registers. + +- interrupts: The list of interrupts that are used for all the pins + managed by this GPIO bank. There can be more than one interrupt + (example: 1 interrupt per 8 pins on Armada XP, which means 4 + interrupts per bank of 32 GPIOs). + +- interrupt-controller: identifies the node as an interrupt controller + +- #interrupt-cells: specifies the number of celles needed to encode an + interrupt source + +- gpio-controller: marks the device node as a gpio controller + +- ngpios: number of GPIOs this controller has + +- #gpio-cells: Should be one. It is the pin number. + +Example: + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + interrupts = <16>, <17>, <18>, <19>; + };
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Gregory Clement <gregory.clement@free-electrons.com> --- .../devicetree/bindings/gpio/gpio-mvebu.txt | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt