diff mbox

[6/9] drm/i915: Add eDP support for Valleyview

Message ID 1348666658-31345-7-git-send-email-vijay.a.purushothaman@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Vijay Purushothaman Sept. 26, 2012, 1:37 p.m. UTC 
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.

v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
	interfaces

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
 2 files changed, 14 insertions(+), 5 deletions(-)

Comments

Daniel Vetter Sept. 26, 2012, 2:31 p.m. UTC | #1 
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> Eventhough Valleyview display block is derived from Cantiga, VLV
> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> 
> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> v3: fix DPIO value calculation to use same values for all display
> 	interfaces
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
>  2 files changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a8a81d1..aee6151 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		}
>  	}
>  
> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> +		pipeconf |= PIPECONF_BPP_6 |
> +			PIPECONF_ENABLE |
> +			I965_PIPECONF_ACTIVE;
> +	}

No.

Jani Nikula and me just figured out that we have a giant mess with 6bpc
dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
papers over issues.

> +
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c111c3f..af57027 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>  
>  	/* Split out the IBX/CPU vs CPT settings */
>  
> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  {
>  	struct drm_device *dev = intel_dp->base.base.dev;
>  
> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_400:
>  			return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  		uint32_t    signal_levels;
>  
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  			break;
>  		}
>  
> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>  		if (intel_dpd_is_edp(dev))
>  			intel_dp->is_pch_edp = true;
>  
> -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> +		type = DRM_MODE_CONNECTOR_eDP;
> +		intel_encoder->type = INTEL_OUTPUT_EDP;

You need to be a notch more careful, since since

commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
Author: Adam Jackson <ajax@redhat.com>
Date:   Fri Jul 16 14:46:29 2010 -0400

    drm/i915: Initialize LVDS and eDP outputs before anything else

We initialize built-in panels before external outputs. Hence you need to
adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
first. A bit a mess, I know.

Cheers, Daniel

> +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>  		type = DRM_MODE_CONNECTOR_eDP;
>  		intel_encoder->type = INTEL_OUTPUT_EDP;
>  	} else {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter Sept. 26, 2012, 2:49 p.m. UTC | #2 
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> > Eventhough Valleyview display block is derived from Cantiga, VLV
> > supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> > 
> > v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> > v3: fix DPIO value calculation to use same values for all display
> > 	interfaces
> > 
> > Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
> >  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
> >  2 files changed, 14 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a8a81d1..aee6151 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >  		}
> >  	}
> >  
> > +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> > +		pipeconf |= PIPECONF_BPP_6 |
> > +			PIPECONF_ENABLE |
> > +			I965_PIPECONF_ACTIVE;
> > +	}
> 
> No.
> 
> Jani Nikula and me just figured out that we have a giant mess with 6bpc
> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> papers over issues.

Forgotten to put Jani on cc.
-Daniel

> 
> > +
> >  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
> >  	drm_mode_debug_printmodeline(mode);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index c111c3f..af57027 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> >  
> >  	/* Split out the IBX/CPU vs CPT settings */
> >  
> > -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
> > +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> >  			intel_dp->DP |= DP_SYNC_HS_HIGH;
> >  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> > @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> >  {
> >  	struct drm_device *dev = intel_dp->base.base.dev;
> >  
> > -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> >  		case DP_TRAIN_VOLTAGE_SWING_400:
> >  			return DP_TRAIN_PRE_EMPHASIS_6;
> > @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >  		uint32_t    signal_levels;
> >  
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >  			break;
> >  		}
> >  
> > -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
> > +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> >  			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> >  			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> >  		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> > @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> >  		if (intel_dpd_is_edp(dev))
> >  			intel_dp->is_pch_edp = true;
> >  
> > -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> > +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
> > +		type = DRM_MODE_CONNECTOR_eDP;
> > +		intel_encoder->type = INTEL_OUTPUT_EDP;
> 
> You need to be a notch more careful, since since
> 
> commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
> Author: Adam Jackson <ajax@redhat.com>
> Date:   Fri Jul 16 14:46:29 2010 -0400
> 
>     drm/i915: Initialize LVDS and eDP outputs before anything else
> 
> We initialize built-in panels before external outputs. Hence you need to
> adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
> first. A bit a mess, I know.
> 
> Cheers, Daniel
> 
> > +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
> >  		type = DRM_MODE_CONNECTOR_eDP;
> >  		intel_encoder->type = INTEL_OUTPUT_EDP;
> >  	} else {
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
Jani Nikula Sept. 27, 2012, 7:18 a.m. UTC | #3 
On Wed, 26 Sep 2012, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a8a81d1..aee6151 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>  		}
>>  	}
>>  
>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>> +		pipeconf |= PIPECONF_BPP_6 |
>> +			PIPECONF_ENABLE |
>> +			I965_PIPECONF_ACTIVE;
>> +	}
>
> No.
>
> Jani Nikula and me just figured out that we have a giant mess with 6bpc
> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> papers over issues.

Vijay, please check commit 0c96c65b in drm-intel-fixes.

BR,
Jani.
Vijay Purushothaman Sept. 27, 2012, 1:38 p.m. UTC | #4 
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
>> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>>> Eventhough Valleyview display block is derived from Cantiga, VLV
>>> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
>>>
>>> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
>>> v3: fix DPIO value calculation to use same values for all display
>>> 	interfaces
>>>
>>> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
>>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
>>> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_display.c |    6 ++++++
>>>   drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
>>>   2 files changed, 14 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index a8a81d1..aee6151 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>>   		}
>>>   	}
>>>
>>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>>> +		pipeconf |= PIPECONF_BPP_6 |
>>> +			PIPECONF_ENABLE |
>>> +			I965_PIPECONF_ACTIVE;
>>> +	}
>>
>> No.
>>
>> Jani Nikula and me just figured out that we have a giant mess with 6bpc
>> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
>> papers over issues.
>
> Forgotten to put Jani on cc.
> -Daniel

Thanks for the catch. I've removed this unconditional enabling of 6bpc 
for VLV eDP. For long term i believe, eDP handling in i9xx_crtc_mode_set 
should be changed along the lines of ironlake_crtc_mode_set for cleaner 
code. For now, this should unblock others with VLV enabling.

>
>>
>>> +
>>>   	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>>>   	drm_mode_debug_printmodeline(mode);
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>>> index c111c3f..af57027 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -885,7 +885,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>>>
>>>   	/* Split out the IBX/CPU vs CPT settings */
>>>
>>> -	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
>>> +	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
>>>   		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>>>   			intel_dp->DP |= DP_SYNC_HS_HIGH;
>>>   		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>>> @@ -1474,7 +1474,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>>   {
>>>   	struct drm_device *dev = intel_dp->base.base.dev;
>>>
>>> -	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>>   		case DP_TRAIN_VOLTAGE_SWING_400:
>>>   			return DP_TRAIN_PRE_EMPHASIS_6;
>>> @@ -1773,7 +1773,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>>>   		uint32_t    signal_levels;
>>>
>>>
>>> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>>>   			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>>>   		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
>>> @@ -1859,7 +1859,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
>>>   			break;
>>>   		}
>>>
>>> -		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
>>> +		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
>>>   			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
>>>   			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
>>>   		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
>>> @@ -2471,7 +2471,10 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
>>>   		if (intel_dpd_is_edp(dev))
>>>   			intel_dp->is_pch_edp = true;
>>>
>>> -	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>>> +	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
>>> +		type = DRM_MODE_CONNECTOR_eDP;
>>> +		intel_encoder->type = INTEL_OUTPUT_EDP;
>>
>> You need to be a notch more careful, since since
>>
>> commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae
>> Author: Adam Jackson <ajax@redhat.com>
>> Date:   Fri Jul 16 14:46:29 2010 -0400
>>
>>      drm/i915: Initialize LVDS and eDP outputs before anything else
>>
>> We initialize built-in panels before external outputs. Hence you need to
>> adjust intel_setup_outputs for vlv eDP, too, so that the eDP output comes
>> first. A bit a mess, I know.

I've changed the detection order in intel_setup_outputs for valleyview. 
In intel_dp_init, I have added a comment to fix this in next patch series.

Thanks,
Vijay

>>
>> Cheers, Daniel
>>
>>> +	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
>>>   		type = DRM_MODE_CONNECTOR_eDP;
>>>   		intel_encoder->type = INTEL_OUTPUT_EDP;
>>>   	} else {
>>> --
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
>
Vijay Purushothaman Sept. 27, 2012, 1:39 p.m. UTC | #5 
On 9/27/2012 12:48 PM, Jani Nikula wrote:
> On Wed, 26 Sep 2012, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index a8a81d1..aee6151 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>>   		}
>>>   	}
>>>
>>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>>> +		pipeconf |= PIPECONF_BPP_6 |
>>> +			PIPECONF_ENABLE |
>>> +			I965_PIPECONF_ACTIVE;
>>> +	}
>>
>> No.
>>
>> Jani Nikula and me just figured out that we have a giant mess with 6bpc
>> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
>> papers over issues.
>
> Vijay, please check commit 0c96c65b in drm-intel-fixes.
>
> BR,
> Jani.
>
Thanks Jani & Daniel for your review. I will send out the v2 of the 
patch set.

Thanks,
Vijay

>
>
Daniel Vetter Sept. 27, 2012, 1:50 p.m. UTC | #6 
On Thu, Sep 27, 2012 at 07:08:41PM +0530, Vijay Purushothaman wrote:
> On 9/26/2012 8:19 PM, Daniel Vetter wrote:
> >On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
> >>On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> >>>Eventhough Valleyview display block is derived from Cantiga, VLV
> >>>supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
> >>>
> >>>v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> >>>v3: fix DPIO value calculation to use same values for all display
> >>>	interfaces
> >>>
> >>>Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> >>>Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> >>>Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> >>>---
> >>>  drivers/gpu/drm/i915/intel_display.c |    6 ++++++
> >>>  drivers/gpu/drm/i915/intel_dp.c      |   13 ++++++++-----
> >>>  2 files changed, 14 insertions(+), 5 deletions(-)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>>index a8a81d1..aee6151 100644
> >>>--- a/drivers/gpu/drm/i915/intel_display.c
> >>>+++ b/drivers/gpu/drm/i915/intel_display.c
> >>>@@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >>>  		}
> >>>  	}
> >>>
> >>>+	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> >>>+		pipeconf |= PIPECONF_BPP_6 |
> >>>+			PIPECONF_ENABLE |
> >>>+			I965_PIPECONF_ACTIVE;
> >>>+	}
> >>
> >>No.
> >>
> >>Jani Nikula and me just figured out that we have a giant mess with 6bpc
> >>dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> >>papers over issues.
> >
> >Forgotten to put Jani on cc.
> >-Daniel
> 
> Thanks for the catch. I've removed this unconditional enabling of
> 6bpc for VLV eDP. For long term i believe, eDP handling in
> i9xx_crtc_mode_set should be changed along the lines of
> ironlake_crtc_mode_set for cleaner code. For now, this should
> unblock others with VLV enabling.

My Big Plan (tm) for handling bpc, bandwidth, dotclocks and clocks in
general (e.g. pll sharing) is to move all this stuff out of the ->mode_set
callbacks and into a new preparation step at the beginning of the modeset
sequence (i.e. before we start touching the hw). Essentially I want to
extend the current ->mode_adjust callbacks and move all these calculations
in there. Aims for this are
- should allow us to move a lot of the encoder specific code that
  currently sits in the xxx_crtc_mode_set functions into encoder callbacks
- allows us to fail a modeset that won't work (e.g. due to pll sharing
  limits or fdi link bw limits) _before_ we touch the hw
- prepares for the global modeset stuff, where we want to make clever
  decision about shared resources (e.g. enable 6bpc dithering if there are
  not enough fdi lanes availbale in 3 pipe configs).

So the ironlake bpc code is a bit cleaner, but imho still gets it wrong.

Cheers, Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4405,6 +4405,12 @@  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		}
 	}
 
+	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		pipeconf |= PIPECONF_BPP_6 |
+			PIPECONF_ENABLE |
+			I965_PIPECONF_ACTIVE;
+	}
+
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c111c3f..af57027 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -885,7 +885,7 @@  intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
+	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1474,7 +1474,7 @@  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
 	struct drm_device *dev = intel_dp->base.base.dev;
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+	if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1773,7 +1773,7 @@  intel_dp_start_link_train(struct intel_dp *intel_dp)
 		uint32_t    signal_levels;
 
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -1859,7 +1859,7 @@  intel_dp_complete_link_train(struct intel_dp *intel_dp)
 			break;
 		}
 
-		if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
+		if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 			signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
 			DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
 		} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
@@ -2471,7 +2471,10 @@  intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
 		if (intel_dpd_is_edp(dev))
 			intel_dp->is_pch_edp = true;
 
-	if (output_reg == DP_A || is_pch_edp(intel_dp)) {
+	if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
+		type = DRM_MODE_CONNECTOR_eDP;
+		intel_encoder->type = INTEL_OUTPUT_EDP;
+	} else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
 		type = DRM_MODE_CONNECTOR_eDP;
 		intel_encoder->type = INTEL_OUTPUT_EDP;
 	} else {