diff mbox

[v2,3/9] drm/i915: Add Valleyview lane control definitions

Message ID 1348753389-30736-4-git-send-email-vijay.a.purushothaman@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Vijay Purushothaman Sept. 27, 2012, 1:43 p.m. UTC 
Added DPIO data lane register definitions for Valleyview

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Jesse Barnes Sept. 27, 2012, 3:17 p.m. UTC | #1 
On Thu, 27 Sep 2012 19:13:03 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> Added DPIO data lane register definitions for Valleyview
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a828e90..3f75ee6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -369,6 +369,7 @@
>  #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
>  #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
>  #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> +#define   DPIO_PLL_REFCLK_SEL_MASK	3
>  #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
>  #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
>  #define _DPIO_REFSFR_B			0x8034
> @@ -384,6 +385,13 @@
>  
>  #define DPIO_FASTCLK_DISABLE		0x8100
>  
> +#define _DPIO_DATA_LANE0		0x0220
> +#define _DPIO_DATA_LANE1		0x0420
> +#define _DPIO_DATA_LANE2		0x2620
> +#define _DPIO_DATA_LANE3		0x2820
> +#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
> +#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
> +
>  /*
>   * Fence registers
>   */

The lane regs don't match what I have in one of my docs (it has 120,
220, 2320, 2420), but I think it's for CDV, so I'll take your word
for it.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828e90..3f75ee6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -369,6 +369,7 @@ 
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
 #define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_PLL_REFCLK_SEL_MASK	3
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
 #define _DPIO_REFSFR_B			0x8034
@@ -384,6 +385,13 @@ 
 
 #define DPIO_FASTCLK_DISABLE		0x8100
 
+#define _DPIO_DATA_LANE0		0x0220
+#define _DPIO_DATA_LANE1		0x0420
+#define _DPIO_DATA_LANE2		0x2620
+#define _DPIO_DATA_LANE3		0x2820
+#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
+#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
+
 /*
  * Fence registers
  */