[07/14] drm/i915: convert CPU M/N timings to transcoder

Message ID	1350595304-18237-8-git-send-email-przanoni@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org> From: Paulo Zanoni <przanoni@gmail.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Oct 2012 18:21:37 -0300 Message-Id: <1350595304-18237-8-git-send-email-przanoni@gmail.com> In-Reply-To: <1350595304-18237-1-git-send-email-przanoni@gmail.com> References: <1350595304-18237-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 07/14] drm/i915: convert CPU M/N timings to transcoder Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org

Message ID

1350595304-18237-8-git-send-email-przanoni@gmail.com (mailing list archive)

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New, archived

Headers

From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Date: Thu, 18 Oct 2012 18:21:37 -0300
Message-Id: <1350595304-18237-8-git-send-email-przanoni@gmail.com>
In-Reply-To: <1350595304-18237-1-git-send-email-przanoni@gmail.com>
References: <1350595304-18237-1-git-send-email-przanoni@gmail.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [Intel-gfx] [PATCH 07/14] drm/i915: convert CPU M/N timings to
	transcoder
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Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org

Commit Message

Paulo Zanoni Oct. 18, 2012, 9:21 p.m. UTC

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
 drivers/gpu/drm/i915/intel_dp.c      | 10 ++++++----
 3 files changed, 20 insertions(+), 18 deletions(-)

Comments

Daniel Vetter Oct. 18, 2012, 10:25 p.m. UTC | #1

On Thu, Oct 18, 2012 at 06:21:37PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Same thing as the previous commits. Not renaming this one since it
> exists since way before Haswell.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Again I think we can drop the fdi hunks here. We better keep the set_m_n
hunks (I think we only need the dp one though), since that part of the
code is a convoluted mess and needs a cleanup. I have plans for pre-hsw
pch platforms ;-)
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 16 ++++++++--------
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
>  drivers/gpu/drm/i915/intel_dp.c      | 10 ++++++----
>  3 files changed, 20 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9eab732..5b4f608 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3304,14 +3304,14 @@
>  #define _PIPEB_LINK_M2           0x61048
>  #define _PIPEB_LINK_N2           0x6104c
>  
> -#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> -#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> -#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> -#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> -#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> -#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> -#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> -#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
> +#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
> +#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
> +#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
> +#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
> +#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
> +#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
> +#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
> +#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
>  
>  /* CPU panel fitter */
>  /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dc93c39..95a4a5f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2689,7 +2689,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>  
>  	/* Write the TU size bits so error detection works */
>  	I915_WRITE(FDI_RX_TUSIZE1(pipe),
> -		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +		   I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
>  
>  	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
>  	reg = FDI_RX_CTL(pipe);
> @@ -4847,7 +4847,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> +	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>  	struct intel_encoder *intel_encoder, *edp_encoder = NULL;
>  	struct fdi_m_n m_n = {0};
>  	int target_clock, pixel_multiplier, lane, link_bw;
> @@ -4910,10 +4910,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
>  	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
>  			     &m_n);
>  
> -	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> -	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> -	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> -	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> +	I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
> +	I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
> +	I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
> +	I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
>  }
>  
>  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 697b176..244cb6a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -791,6 +791,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
>  	int lane_count = 4;
>  	struct intel_dp_m_n m_n;
>  	int pipe = intel_crtc->pipe;
> +	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
>  
>  	/*
>  	 * Find the lane count in the intel_encoder private
> @@ -815,10 +816,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
>  			     mode->clock, adjusted_mode->clock, &m_n);
>  
>  	if (IS_HASWELL(dev)) {
> -		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> -		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> -		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> -		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
> +		I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
> +			   TU_SIZE(m_n.tu) | m_n.gmch_m);
> +		I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
> +		I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
> +		I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
>  	} else if (HAS_PCH_SPLIT(dev)) {
>  		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
>  		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
> -- 
> 1.7.11.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9eab732..5b4f608 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3304,14 +3304,14 @@ 
 #define _PIPEB_LINK_M2           0x61048
 #define _PIPEB_LINK_N2           0x6104c
 
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
 
 /* CPU panel fitter */
 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc93c39..95a4a5f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2689,7 +2689,7 @@  static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
 
 	/* Write the TU size bits so error detection works */
 	I915_WRITE(FDI_RX_TUSIZE1(pipe),
-		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
+		   I915_READ(PIPE_DATA_M1(cpu_transcoder)) & TU_SIZE_MASK);
 
 	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
 	reg = FDI_RX_CTL(pipe);
@@ -4847,7 +4847,7 @@  static void ironlake_set_m_n(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 	struct intel_encoder *intel_encoder, *edp_encoder = NULL;
 	struct fdi_m_n m_n = {0};
 	int target_clock, pixel_multiplier, lane, link_bw;
@@ -4910,10 +4910,10 @@  static void ironlake_set_m_n(struct drm_crtc *crtc,
 	ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
 			     &m_n);
 
-	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+	I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
+	I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+	I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+	I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 }
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 697b176..244cb6a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -791,6 +791,7 @@  intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 	int lane_count = 4;
 	struct intel_dp_m_n m_n;
 	int pipe = intel_crtc->pipe;
+	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 
 	/*
 	 * Find the lane count in the intel_encoder private
@@ -815,10 +816,11 @@  intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 			     mode->clock, adjusted_mode->clock, &m_n);
 
 	if (IS_HASWELL(dev)) {
-		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
-		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
-		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
-		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+		I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
+			   TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);

[07/14] drm/i915: convert CPU M/N timings to transcoder

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