| Message ID | 1352251597-2936-1-git-send-email-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Nov 07, 2012 at 02:26:37AM +0100, Joseph Lo wrote: > Enable the data prefetch on L2. The bit28 in aux ctrl register. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Cheers, Peter.
On 11/06/2012 06:26 PM, Joseph Lo wrote:
> Enable the data prefetch on L2. The bit28 in aux ctrl register.
Applied to Tegra's for-3.8/soc branch. Thanks.
On Wed, Nov 07, 2012 at 02:26:37AM +0100, Joseph Lo wrote: > Enable the data prefetch on L2. The bit28 in aux ctrl register. > > Signed-off-by: Joseph Lo <josephl@nvidia.com> > --- > arch/arm/mach-tegra/common.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c > index c25746e..c3dee56 100644 > --- a/arch/arm/mach-tegra/common.c > +++ b/arch/arm/mach-tegra/common.c > @@ -124,7 +124,7 @@ static void __init tegra_init_cache(void) > > cache_type = readl(p + L2X0_CACHE_TYPE); > aux_ctrl = (cache_type & 0x700) << (17-8); > - aux_ctrl |= 0x6C000001; > + aux_ctrl |= 0x7C000001; Just found out that we should also set bit 22 as per http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395%2F1 Stephen, should I send a seperate patch for that? Cheers, Peter.
On 11/12/2012 05:19 AM, Peter De Schrijver wrote: > On Wed, Nov 07, 2012 at 02:26:37AM +0100, Joseph Lo wrote: >> Enable the data prefetch on L2. The bit28 in aux ctrl register. >> >> Signed-off-by: Joseph Lo <josephl@nvidia.com> >> --- >> arch/arm/mach-tegra/common.c | 2 +- >> 1 files changed, 1 insertions(+), 1 deletions(-) >> >> diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c >> index c25746e..c3dee56 100644 >> --- a/arch/arm/mach-tegra/common.c >> +++ b/arch/arm/mach-tegra/common.c >> @@ -124,7 +124,7 @@ static void __init tegra_init_cache(void) >> >> cache_type = readl(p + L2X0_CACHE_TYPE); >> aux_ctrl = (cache_type & 0x700) << (17-8); >> - aux_ctrl |= 0x6C000001; >> + aux_ctrl |= 0x7C000001; > > Just found out that we should also set bit 22 as per > http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6395%2F1 > > Stephen, should I send a seperate patch for that? Yes please; I've applied the patch in this thread already.
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index c25746e..c3dee56 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -124,7 +124,7 @@ static void __init tegra_init_cache(void) cache_type = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (cache_type & 0x700) << (17-8); - aux_ctrl |= 0x6C000001; + aux_ctrl |= 0x7C000001; ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); if (!ret)
Enable the data prefetch on L2. The bit28 in aux ctrl register. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm/mach-tegra/common.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)