| Message ID | 1359047682.21576.154.camel@gandalf.local.home (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jan 24, 2013 at 6:14 PM, Steven Rostedt <rostedt@goodmis.org> wrote: > I tried to get my snowball board working on the latest kernel, but it > locks up hard very early on boot up. > > I bisected it down to this commit: > > commit ebc96db7632f987e0b9bffcb782cf5cfb8afb0dd > Author: Ulf Hansson <ulf.hansson@linaro.org> > Date: Mon Aug 27 15:45:53 2012 +0200 > > ARM: ux500: Switch to use common clock framework Yeah the new common clock framework is a bit like a heart transplant on the platforms you convert, some fallout is expected. However I thought we had all the clk fixes covered by -rc4 :-( I don't have a Snowball right now myself, so have to ask for help here (non snowball ux500's work just fine for me). Lee, are you still booting the Snowball on new kernels everyday, and do you know if some fix is still missing? Yours, Linus Walleij
> > I tried to get my snowball board working on the latest kernel, but it > > locks up hard very early on boot up. > > > > I bisected it down to this commit: > > > > commit ebc96db7632f987e0b9bffcb782cf5cfb8afb0dd > > Author: Ulf Hansson <ulf.hansson@linaro.org> > > Date: Mon Aug 27 15:45:53 2012 +0200 > > > > ARM: ux500: Switch to use common clock framework > > Yeah the new common clock framework is a bit like a heart > transplant on the platforms you convert, some fallout is expected. > > However I thought we had all the clk fixes covered by -rc4 :-( > > I don't have a Snowball right now myself, so have to ask > for help here (non snowball ux500's work just fine for me). > > Lee, are you still booting the Snowball on new kernels > everyday, and do you know if some fix is still missing? Can you provide your bootlog please Steven?
On Wed, 2013-01-30 at 09:01 +0000, Lee Jones wrote: > Can you provide your bootlog please Steven? > Here's the bootlog after I reverted the patch and successfully booted: Card did not respond to voltage select! smc911x: detected LAN9221 controller smc911x: phy initialized smc911x: MAC 46:36:d8:d6:64:4c BOOTP broadcast 1 BOOTP broadcast 2 *** Unhandled DHCP Option in OFFER/ACK: 2 *** Unhandled DHCP Option in OFFER/ACK: 28 *** Unhandled DHCP Option in OFFER/ACK: 2 *** Unhandled DHCP Option in OFFER/ACK: 28 DHCP client bound to address 192.168.23.75 Using smc911x-0 device TFTP from server 192.168.23.10; our IP address is 192.168.23.75 Filename 'snowball/image'. Load address: 0x100000 Loading: *################################################################# ################################################################# ################################################################# ################################################################# ################################## done Bytes transferred = 4315824 (41dab0 hex) ## Booting kernel from Legacy Image at 00100000 ... Image Name: Linux-3.8.0-rc4-test+ Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 4315760 Bytes = 4.1 MB Load Address: 00008000 Entry Point: 00008000 Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0x300 [ 0.000000] Linux version 3.8.0-rc4-test+ (rostedt@goliath) (gcc version 4.5.2 (GCC) ) #278 SMP PREEMPT Thu Jan 24 11:54:10 EST 2013 [ 0.000000] CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Calao Systems Snowball platform [ 0.000000] Ignoring unrecognised tag 0x41000403 [ 0.000000] Memory policy: ECC disabled, Data cache writealloc [ 0.000000] DB8500 v2.1 [0x008500b1] [ 0.000000] PERCPU: Embedded 9 pages/cpu @c1162000 s13376 r8192 d15296 u36864 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 206848 [ 0.000000] Kernel command line: console=ttyAMA2,115200n8 vmalloc=256M root=/dev/mmcblk0p3 rootwait mem=128M@0 mali.mali_mem=32M@128M hwmem=168M@160M mem=48M@328M mem_issw=1M@383M mem=640M@384M [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] __ex_table already sorted, skipping sort [ 0.000000] Memory: 128MB 48MB 640MB = 816MB total [ 0.000000] Memory: 818568k/818568k available, 17016k reserved, 278528K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xef800000 - 0xff000000 ( 248 MB) [ 0.000000] lowmem : 0xc0000000 - 0xef000000 ( 752 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc0822024 (8297 kB) [ 0.000000] .init : 0xc0823000 - 0xc0871440 ( 314 kB) [ 0.000000] .data : 0xc0872000 - 0xc08cc5d0 ( 362 kB) [ 0.000000] .bss : 0xc08cc5d0 - 0xc095a880 ( 569 kB) [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] PRCMU firmware: U8500, version 3.4.9 [ 0.000000] MTU0 clock rate: 133330000 Hz [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] Console: colour dummy device 80x30 [ 0.000488] Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816) [ 0.090179] pid_max: default: 32768 minimum: 301 [ 0.090393] Security Framework initialized [ 0.090484] AppArmor: AppArmor initialized [ 0.090606] Mount-cache hash table entries: 512 [ 0.091705] Initializing cgroup subsys cpuacct [ 0.091796] CPU: Testing write buffer coherency: ok [ 0.091888] ftrace: allocating 20559 entries in 61 pages [ 0.137756] CPU0: thread -1, cpu 0, socket 3, mpidr 80000300 [ 0.137878] Setting up static identity map for 0x5b6450 - 0x5b64a8 [ 0.137939] L310 cache controller enabled [ 0.137969] l2x0: 8 ways, CACHE_ID 0x000000c0, AUX_CTRL 0x7ec60800, Cache size: 524288 B [ 0.238708] CPU1: Booted secondary processor [ 0.313140] CPU1: thread -1, cpu 1, socket 3, mpidr 80000301 [ 0.313201] Brought up 2 CPUs [ 0.313201] SMP: Total of 2 processors activated (3588.09 BogoMIPS). [ 0.313934] devtmpfs: initialized [ 0.318908] pinctrl core: initialized pinctrl subsystem [ 0.320159] regulator-dummy: no parameters [ 0.321075] NET: Registered protocol family 16 [ 0.321960] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.325164] gpio gpio.0: at address f812e000 [ 0.326019] gpio gpio.1: at address f812e080 [ 0.326812] gpio gpio.2: at address f800e000 [ 0.327667] gpio gpio.3: at address f800e080 [ 0.328460] gpio gpio.4: at address f800e100 [ 0.329315] gpio gpio.5: at address f800e180 [ 0.330200] gpio gpio.6: at address f811e000 [ 0.331054] gpio gpio.7: at address f811e080 [ 0.331939] gpio gpio.8: at address fa3fe000 [ 0.333099] pinctrl-nomadik pinctrl-db8500: initialized Nomadik pin control driver [ 0.334991] ab8500-core ab8500-core.0: detected chip, AB8500 rev. 3.0 [ 0.335052] ab8500-core ab8500-core.0: switch off cause(s) (0x20): [ 0.335052] "Battery level lower than power on reset threshold" [ 0.341369] DB8500 PRCMU initialized [ 0.344024] mop500_audio_init: Register platform-device 'snd-soc-mop500'. [ 0.344238] Initialize MSP I2S-devices. [ 0.344268] Register platform-device 'ux500-msp-i2s', id 0, irq 63 [ 0.344451] Register platform-device 'ux500-msp-i2s', id 1, irq 94 [ 0.344665] Register platform-device 'ux500-msp-i2s', id 2, irq 130 [ 0.344848] Register platform-device 'ux500-msp-i2s', id 3, irq 94 [ 0.345764] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.345794] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.346343] db8500-vape: no parameters [ 0.346679] db8500-varm: no parameters [ 0.346984] db8500-vmodem: no parameters [ 0.347259] db8500-vpll: no parameters [ 0.347534] db8500-vsmps1: no parameters [ 0.347808] db8500-vsmps2: no parameters [ 0.348114] db8500-vsmps3: no parameters [ 0.348388] db8500-vrf1: no parameters [ 0.348724] db8500-sva-mmdsp: no parameters [ 0.348999] db8500-sva-mmdsp-ret: no parameters [ 0.349273] db8500-sva-pipe: no parameters [ 0.349578] db8500-sia-mmdsp: no parameters [ 0.349853] db8500-sia-mmdsp-ret: no parameters [ 0.350128] db8500-sia-pipe: no parameters [ 0.350433] db8500-sga: no parameters [ 0.350463] db8500-sga: supplied by db8500-vape [ 0.351135] db8500-b2r2-mcde: no parameters [ 0.351165] db8500-b2r2-mcde: supplied by db8500-vape [ 0.351531] db8500-esram12: no parameters [ 0.351837] db8500-esram12-ret: no parameters [ 0.352111] db8500-esram34: no parameters [ 0.352386] db8500-esram34-ret: no parameters [ 0.352691] Serial: AMBA PL011 UART driver [ 0.352874] uart0: ttyAMA0 at MMIO 0x80120000 (irq = 43) is a PL011 rev3 [ 0.353424] uart1: ttyAMA1 at MMIO 0x80121000 (irq = 51) is a PL011 rev3 [ 0.353912] uart2: ttyAMA2 at MMIO 0x80007000 (irq = 58) is a PL011 rev3 [ 0.901672] console [ttyAMA2] enabled [ 0.926879] bio: create slab <bio-0> at 0 [ 0.931762] dma40 dma40.0: hardware revision: 3 @ 0x801c0000 [ 0.937469] dma40 dma40.0: 7 of 8 physical DMA channels available [ 0.943603] dma40 dma40.0: [d40_phy_res_init] INFO: channel 4 is misconfigured (0) [ 0.951171] dma40 dma40.0: [d40_phy_res_init] INFO: channel 5 is misconfigured (0) [ 0.958740] dma40 dma40.0: [d40_phy_res_init] INFO: channel 6 is misconfigured (0) [ 0.982788] dma40 dma40.0: initialized [ 0.987060] EN-3V3: Failed to request enable GPIO337: -517 [ 0.992767] reg-fixed-voltage reg-fixed-voltage.1: Failed to register regulator: -517 [ 1.000610] platform reg-fixed-voltage.1: Driver reg-fixed-voltage requests probe deferral [ 1.010345] V-DISPLAY: 2500 <--> 2900 mV at 2500 mV [ 1.015777] V-eMMC1: 1100 <--> 3300 mV at 2900 mV [ 1.020935] V-MMC-SD: 1200 <--> 2910 mV at 2910 mV [ 1.026184] V-INTCORE: at 1250 mV [ 1.030029] V-TVOUT: 2000 mV [ 1.033294] LDO-USB: 3300 mV [ 1.036529] V-AUD: 2000 mV [ 1.039672] V-AMIC1: 2050 mV [ 1.042907] V-AMIC2: 2050 mV [ 1.046173] V-DMIC: 1800 mV [ 1.049346] V-CSI/DSI: 1200 mV [ 1.052551] V-CSI/DSI: Failed to create debugfs directory [ 1.060028] SCSI subsystem initialized [ 1.063842] ssp-pl022 ssp0: ARM PL022 driver, device ID: 0x01080022 [ 1.070190] ssp-pl022 ssp0: could not get default pinstate [ 1.075714] pl022: mapped registers from 0x80002000 to ef860000 [ 1.081726] ssp-pl022 ssp0: setup for DMA on RX dma0chan0, TX dma0chan1 [ 1.089843] usbcore: registered new interface driver usbfs [ 1.095520] usbcore: registered new interface driver hub [ 1.101043] usbcore: registered new device driver usb [ 1.106353] ab8500-usb ab8500-usb.0: AB8500 usb driver initialized [ 1.113372] nmk-i2c nmk-i2c.0: initialize Nomadik I2C0 at [mem 0x80004000-0x80004fff] on virtual base ef862000 [ 1.123748] nmk-i2c nmk-i2c.1: initialize Nomadik I2C1 at [mem 0x80122000-0x80122fff] on virtual base ef864000 [ 1.134094] nmk-i2c nmk-i2c.2: initialize Nomadik I2C2 at [mem 0x80128000-0x80128fff] on virtual base ef866000 [ 1.144439] nmk-i2c nmk-i2c.3: initialize Nomadik I2C3 at [mem 0x80110000-0x80110fff] on virtual base ef868000 [ 1.155792] Advanced Linux Sound Architecture Driver Initialized. [ 1.162902] Bluetooth: Core ver 2.16 [ 1.166717] NET: Registered protocol family 31 [ 1.171142] Bluetooth: HCI device and connection manager initialized [ 1.177520] Bluetooth: HCI socket layer initialized [ 1.182403] Bluetooth: L2CAP socket layer initialized [ 1.187469] Bluetooth: SCO socket layer initialized [ 1.192901] cfg80211: Calling CRDA to update world regulatory domain [ 1.199432] NetLabel: Initializing [ 1.202880] NetLabel: domain hash size = 128 [ 1.207244] NetLabel: protocols = UNLABELED CIPSOv4 [ 1.212249] NetLabel: unlabeled traffic allowed by default [ 1.219024] ab8500-charger ab8500-charger.0: falling back to legacy platform data [ 1.226623] ab8500-charger ab8500-charger.0: failed to get vddadc regulator [ 1.233673] platform ab8500-charger.0: Driver ab8500-charger requests probe deferral [ 1.241668] ab8500-btemp ab8500-btemp.0: falling back to legacy platform data [ 1.248992] ab8500-btemp ab8500-btemp.0: No fg found [ 1.253997] ab8500-btemp ab8500-btemp.0: ab8500_btemp_id get batctrl res failed [ 1.261291] ab8500-btemp ab8500-btemp.0: failed to identify the battery [ 1.277252] ab8500-fg ab8500-fg.0: falling back to legacy platform data [ 1.289733] Switching to clocksource dbx500-prcmu-timer [ 1.319610] AppArmor: AppArmor Filesystem Enabled [ 1.353912] NET: Registered protocol family 2 [ 1.359039] TCP established hash table entries: 8192 (order: 4, 65536 bytes) [ 1.366210] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) [ 1.372833] TCP: Hash tables configured (established 8192 bind 8192) [ 1.379425] TCP: reno registered [ 1.382659] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 1.388671] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 1.395355] NET: Registered protocol family 1 [ 1.400573] NetWinder Floating Point Emulator V0.97 (double precision) [ 1.407196] CPU PMU: probing PMU on CPU 0 [ 1.411224] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available [ 1.420837] audit: initializing netlink socket (disabled) [ 1.426269] type=2000 audit(1.130:1): initialized [ 1.445343] bounce pool size: 64 pages [ 1.449371] VFS: Disk quotas dquot_6.5.2 [ 1.453430] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 1.460632] 9p: Installing v9fs 9p2000 file system support [ 1.466156] msgmni has been set to 1054 [ 1.471069] io scheduler noop registered [ 1.474975] io scheduler deadline registered (default) [ 1.480285] io scheduler cfq registered [ 1.485229] uart-pl011 uart0: DMA channel TX dma0chan2 [ 1.490417] uart-pl011 uart0: DMA channel RX dma0chan3 [ 1.495544] uart-pl011 uart1: DMA channel TX dma0chan4 [ 1.500732] uart-pl011 uart1: DMA channel RX dma0chan5 [ 1.505889] uart-pl011 uart2: DMA channel TX dma0chan6 [ 1.511047] uart-pl011 uart2: DMA channel RX dma0chan7 [ 1.516540] [drm] Initialized drm 1.1.0 20060810 [ 1.532897] brd: module loaded [ 1.542419] loop: module loaded [ 1.546844] tun: Universal TUN/TAP device driver, 1.6 [ 1.551940] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> [ 1.558898] smsc911x: Driver version 2008-10-21 [ 1.563537] smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517 [ 1.570434] smsc911x smsc911x.0 (unregistered net_device): couldn't get regulators -517 [ 1.578552] platform smsc911x.0: Driver smsc911x requests probe deferral [ 1.585449] PPP generic driver version 2.4.2 [ 1.590209] PPP MPPE Compression module registered [ 1.595642] usbcore: registered new interface driver cdc_acm [ 1.601348] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters [ 1.609405] Initializing USB Mass Storage driver... [ 1.614501] usbcore: registered new interface driver usb-storage [ 1.620574] USB Mass Storage support registered. [ 1.625183] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host) [ 1.633972] input: AB8500 POn(PowerOn) Key as /devices/soc0/db8500-prcmu.0/ab8500-core.0/ab8500-poweron-key.0/input/input0 [ 1.662811] ab8500-rtc ab8500-rtc.0: rtc core: registered ab8500-rtc as rtc0 [ 1.670257] i2c /dev entries driver [ 1.675018] ab8500-chargalg ab8500-chargalg.0: falling back to legacy platform data [ 1.683166] ab8500-chargalg ab8500-chargalg.0: probe success [ 1.689331] device-mapper: uevent: version 1.0.3 [ 1.694274] device-mapper: ioctl: 4.23.1-ioctl (2012-12-18) initialised: dm-devel@redhat.com [ 1.702789] Bluetooth: HCI UART driver ver 2.2 [ 1.707336] cpufreq for DB8500 started [ 1.711151] db8500-cpufreq : Failed to get armss clk [ 1.716125] db8500-cpufreq : Failed to get armss clk [ 1.721435] cpuidle: using governor ladder [ 1.725677] cpuidle: using governor menu [ 1.730682] mmci-pl18x sdi4: Provided ocr_mask/setpower will not be used (using regulator instead) [ 1.739746] mmci-pl18x sdi4: mmc0: PL180 manf 80 rev4 at 0x80114000 irq 131,0 (pio) [ 1.747497] mmci-pl18x sdi4: DMA channels RX dma0chan24, TX dma0chan25 [ 1.785675] mmci-pl18x sdi0: Provided ocr_mask/setpower will not be used (using regulator instead) [ 1.794799] mmci-pl18x sdi0: mmc1: PL180 manf 80 rev4 at 0x80126000 irq 92,0 (pio) [ 1.802520] mmci-pl18x sdi0: DMA channels RX dma0chan26, TX dma0chan27 [ 1.846679] usbcore: registered new interface driver usbhid [ 1.852325] usbhid: USB HID core driver [ 1.857025] usbcore: registered new interface driver snd-usb-audio [ 1.864257] Netfilter messages via NETLINK v0.30. [ 1.869110] nf_conntrack version 0.5.0 (12790 buckets, 51160 max) [ 1.875488] ctnetlink v0.93: registering with nfnetlink. [ 1.881256] ip_tables: (C) 2000-2006 Netfilter Core Team [ 1.886688] TCP: cubic registered [ 1.890197] NET: Registered protocol family 10 [ 1.895446] NET: Registered protocol family 17 [ 1.900085] NET: Registered protocol family 15 [ 1.904724] Bluetooth: RFCOMM TTY layer initialized [ 1.909729] Bluetooth: RFCOMM socket layer initialized [ 1.914886] Bluetooth: RFCOMM ver 1.11 [ 1.918731] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 1.924072] Bluetooth: BNEP filters: protocol multicast [ 1.929351] mmc0: new high speed MMC card at address 0001 [ 1.929382] Bluetooth: BNEP socket layer initialized [ 1.929382] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 1.929382] Bluetooth: HIDP socket layer initialized [ 1.929412] NET: Registered protocol family 35 [ 1.955078] 9pnet: Installing 9P2000 support [ 1.955749] mmcblk0: mmc0:0001 3.53 GiB [ 1.955963] mmcblk0boot0: mmc0:0001 partition 1 2.00 MiB [ 1.956176] mmcblk0boot1: mmc0:0001 partition 2 2.00 MiB [ 1.956390] mmcblk0rpmb: mmc0:0001 partition 3 128 KiB [ 1.979492] NET: Registered protocol family 37 [ 1.984069] Key type dns_resolver registered [ 1.984100] mmcblk0: p1 p2 p3 [ 1.991577] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 2 [ 1.999481] Registering SWP/SWPB emulation handler [ 2.007751] LDO-USB: disabling [ 2.010925] db8500-esram34: disabling [ 2.014648] db8500-esram12: disabling [ 2.018890] EN-3V3: Failed to request enable GPIO337: -517 [ 2.024597] input: gpio-keys as /devices/soc0/gpio-keys/input/input1 [ 2.024658] reg-fixed-voltage reg-fixed-voltage.1: Failed to register regulator: -517 [ 2.024688] platform reg-fixed-voltage.1: Driver reg-fixed-voltage requests probe deferral [ 2.024780] ab8500-charger ab8500-charger.0: falling back to legacy platform data [ 2.024963] ab8500-charger ab8500-charger.0: failed to get vddadc regulator [ 2.024993] platform ab8500-charger.0: Driver ab8500-charger requests probe deferral [ 2.025054] smsc911x: Driver version 2008-10-21 [ 2.025146] smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517 [ 2.025146] smsc911x smsc911x.0 (unregistered net_device): couldn't get regulators -517 [ 2.025177] platform smsc911x.0: Driver smsc911x requests probe deferral [ 2.095001] mmcblk0boot1: unknown partition table [ 2.100128] EN-3V3: Failed to request enable GPIO337: -517 [ 2.106201] reg-fixed-voltage reg-fixed-voltage.1: Failed to register regulator: -517 [ 2.114379] platform reg-fixed-voltage.1: Driver reg-fixed-voltage requests probe deferral [ 2.122802] ab8500-charger ab8500-charger.0: falling back to legacy platform data [ 2.122833] ab8500-rtc ab8500-rtc.0: setting system clock to 2013-01-24 17:10:21 UTC (1359047421) [ 2.122955] ALSA device list: [ 2.122955] No soundcards found. [ 2.145721] mmcblk0boot0: unknown partition table [ 2.150878] ab8500-charger ab8500-charger.0: failed to get vddadc regulator [ 2.158020] platform ab8500-charger.0: Driver ab8500-charger requests probe deferral [ 2.165832] smsc911x: Driver version 2008-10-21 [ 2.170532] smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517 [ 2.176910] smsc911x smsc911x.0 (unregistered net_device): couldn't get regulators -517 [ 2.184967] platform smsc911x.0: Driver smsc911x requests probe deferral [ 2.185119] EXT3-fs (mmcblk0p3): error: couldn't mount because of unsupported optional features (240) [ 2.186431] EXT2-fs (mmcblk0p3): error: couldn't mount because of unsupported optional features (244) [ 2.210479] EN-3V3: Failed to request enable GPIO337: -517 [ 2.216278] reg-fixed-voltage reg-fixed-voltage.1: Failed to register regulator: -517 [ 2.224121] platform reg-fixed-voltage.1: Driver reg-fixed-voltage requests probe deferral [ 2.604156] EXT4-fs (mmcblk0p3): warning: maximal mount count reached, running e2fsck is recommended [ 2.618927] EXT4-fs (mmcblk0p3): recovery complete [ 2.631408] EXT4-fs (mmcblk0p3): mounted filesystem with ordered data mode. Opts: (null) [ 2.639587] VFS: Mounted root (ext4 filesystem) on device 179:3. [ 2.650085] devtmpfs: mounted [ 2.653350] Freeing init memory: 312K [ 3.095977] init: ureadahead main process (692) terminated with status 5 [ 3.983581] mmci-pl18x sdi4: error during DMA transfer! [ 3.988952] mmcblk0rpmb: error -110 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 3.998840] mmcblk0rpmb: retrying using single block read [ 4.412017] mmci-pl18x sdi4: error during DMA transfer! [ 4.417358] mmcblk0rpmb: error -110 transferring data, sector 8, nr 8, cmd response 0x900, card status 0xb00 [ 4.427429] mmcblk0rpmb: retrying using single block read [ 4.842041] mmci-pl18x sdi4: error during DMA transfer! [ 4.847381] mmcblk0rpmb: error -110 transferring data, sector 24, nr 8, cmd response 0x900, card status 0xb00 [ 4.857360] mmcblk0rpmb: retrying using single block read [ 5.272949] mmci-pl18x sdi4: error during DMA transfer! [ 5.278289] mmcblk0rpmb: error -110 transferring data, sector 56, nr 8, cmd response 0x900, card status 0xb00 [ 5.288269] mmcblk0rpmb: retrying using single block read [ 5.703063] mmci-pl18x sdi4: error during DMA transfer! [ 5.708404] mmcblk0rpmb: error -110 transferring data, sector 120, nr 8, cmd response 0x900, card status 0xb00 [ 5.718475] mmcblk0rpmb: retrying using single block read [ 6.132965] mmci-pl18x sdi4: error during DMA transfer! [ 6.138336] mmcblk0rpmb: error -110 transferring data, sector 64, nr 8, cmd response 0x900, card status 0xb00 [ 6.148315] mmcblk0rpmb: retrying using single block read [ 6.563507] mmci-pl18x sdi4: error during DMA transfer! [ 6.568847] mmcblk0rpmb: error -110 transferring data, sector 16, nr 8, cmd response 0x900, card status 0xb00 [ 6.579071] mmcblk0rpmb: retrying using single block read [ 6.994110] mmci-pl18x sdi4: error during DMA transfer! [ 6.999450] mmcblk0rpmb: error -110 transferring data, sector 128, nr 8, cmd response 0x900, card status 0xb00 [ 7.009521] mmcblk0rpmb: retrying using single block read [ 7.424499] mmci-pl18x sdi4: error during DMA transfer! [ 7.429870] mmcblk0rpmb: error -110 transferring data, sector 32, nr 8, cmd response 0x900, card status 0xb00 [ 7.439819] mmcblk0rpmb: retrying using single block read [ 7.472686] mmcblk0boot0: r/w command failed, status = 0x80000900 [ 7.478851] end_request: I/O error, dev mmcblk0boot0, sector 3832 [ 7.484954] Buffer I/O error on device mmcblk0boot0, logical block 479 * Starting mDNS/DNS-SD daemon[74G[ OK ] * Starting configure network device security[74G[ OK ] [ 11.248016] mmci-pl18x sdi4: error during DMA transfer! [ 11.253417] mmcblk0rpmb: error -110 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 11.792541] mmci-pl18x sdi4: error during DMA transfer! [ 11.797973] mmcblk0rpmb: error -110 transferring data, sector 24, nr 8, cmd response 0x900, card status 0xb00 [ 12.237579] mmci-pl18x sdi4: error during DMA transfer! [ 12.242980] mmcblk0rpmb: error -110 transferring data, sector 8, nr 8, cmd response 0x900, card status 0xb00 * Starting Mount network filesystems[74G[ OK ] * Starting Upstart job to start rpcbind on boot only[74G[ OK ] * Starting Failsafe Boot Delay[74G[ OK ] * Stopping Upstart job to start rpcbind on boot only[74G[ OK ] * Starting Bridge socket events into upstart[74G[ OK ] [ 12.788513] mmci-pl18x sdi4: error during DMA transfer! [ 12.793945] mmcblk0rpmb: error -110 transferring data, sector 56, nr 8, cmd response 0x900, card status 0xb00 [ 12.823486] mmcblk0boot0: r/w command failed, status = 0x80000900 [ 12.836425] end_request: I/O error, dev mmcblk0boot0, sector 3832 [ 12.842529] Buffer I/O error on device mmcblk0boot0, logical block 479 * Stopping Mount network filesystems[74G[ OK ] * Starting RPC portmapper replacement[74G[ OK ] * Starting Start this job to wait until rpcbind is started or fails to start[74G[ OK ] * Stopping Start this job to wait until rpcbind is started or fails to start[74G[ OK ] * Stopping rpcsec_gss daemon[74G[ OK ] [ 13.397216] mmci-pl18x sdi4: error during DMA transfer! [ 13.402618] mmcblk0rpmb: error -110 transferring data, sector 120, nr 8, cmd response 0x900, card status 0xb00 [ 14.008239] mmci-pl18x sdi4: error during DMA transfer! [ 14.013610] mmcblk0rpmb: error -110 transferring data, sector 64, nr 8, cmd response 0x900, card status 0xb00 [ 14.463684] mmci-pl18x sdi4: error during DMA transfer! [ 14.469177] mmcblk0rpmb: error -110 transferring data, sector 16, nr 8, cmd response 0x900, card status 0xb00 [ 14.911254] mmci-pl18x sdi4: error during DMA transfer! [ 14.916625] mmcblk0rpmb: error -110 transferring data, sector 128, nr 8, cmd response 0x900, card status 0xb00 [ 15.366241] mmci-pl18x sdi4: error during DMA transfer! [ 15.371612] mmcblk0rpmb: error -110 transferring data, sector 32, nr 8, cmd response 0x900, card status 0xb00 [ 15.831939] mmci-pl18x sdi4: error during DMA transfer! [ 15.837341] mmcblk0rpmb: error -110 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 * Starting NSM status monitor[74G[ OK ] * Stopping Failsafe Boot Delay[74G[ OK ] * Starting System V initialisation compatibility[74G[ OK ] * Starting configure network device[74G[ OK ] * Stopping cold plug devices[74G[ OK ] * Stopping log initial device creation[74G[ OK ] [ 16.339935] gadget: no file given for LUN0 [ 16.417297] g_multi musb-hdrc.0.auto: failed to start g_multi: -22 Last login: Thu Jan 24 17:09:11 UTC 2013 on tty1 speech-dispatcher disabled; edit /etc/default/speech-dispatcher Checking for running unattended-upgrades: Welcome to Linaro 12.02 (GNU/Linux 3.8.0-rc4-test+ armv7l) * Documentation: https://wiki.linaro.org/ New release '12.04.1 LTS' available. Run 'do-release-upgrade' to upgrade to it. *** /dev/mmcblk0p3 will be checked for errors at next reboot *** * Starting bluetooth [80G root@linaro-ubuntu-desktop:~# [74G[ OK ] [33m*[39;49m PulseAudio configured for per-user sessions saned disabled; edit /etc/default/saned -- Steve
On Wed, 2013-01-30 at 08:14 -0500, Steven Rostedt wrote: > On Wed, 2013-01-30 at 09:01 +0000, Lee Jones wrote: > > > Can you provide your bootlog please Steven? > > > > Here's the bootlog after I reverted the patch and successfully booted: > And here's the bootlog before I reverted. Actually, this log is from my bisect log, where it found the bad commit: tartup failed EMMC: 0, MMC: 1 In: serial Out: serial Err: serial Net: smc911x-0 Hit any key to stop autoboot: 3 2 1 0 Card did not respond to voltage select! smc911x: detected LAN9221 controller smc911x: phy initialized smc911x: MAC 46:36:d8:d6:64:4c BOOTP broadcast 1 BOOTP broadcast 2 *** Unhandled DHCP Option in OFFER/ACK: 2 *** Unhandled DHCP Option in OFFER/ACK: 28 *** Unhandled DHCP Option in OFFER/ACK: 2 *** Unhandled DHCP Option in OFFER/ACK: 28 DHCP client bound to address 192.168.23.75 Using smc911x-0 device TFTP from server 192.168.23.10; our IP address is 192.168.23.75 Filename 'snowball/image'. Load address: 0x100000 Loading: *################################################################# ################################################################# ################################################################# ################################################################# ######################## done Bytes transferred = 4169048 (3f9d58 hex) ## Booting kernel from Legacy Image at 00100000 ... Image Name: Linux-3.6.0-rc3-test+ Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 4168984 Bytes = 4 MB Load Address: 00008000 Entry Point: 00008000 Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. [ 0.000000] Booting Linux on physical CPU 0 [ 0.000000] Linux version 3.6.0-rc3-test+ (rostedt@goliath) (gcc version 4.5.2 (GCC) ) #272 SMP PREEMPT Thu Jan 24 09:37:12 EST 2013 [ 0.000000] CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Calao Systems Snowball platform [ 0.000000] Ignoring unrecognised tag 0x41000403 [ 0.000000] Memory policy: ECC disabled, Data cache writealloc [ 0.000000] DB8500 v2.1 [0x008500b1] [ 0.000000] PERCPU: Embedded 9 pages/cpu @c1111000 s13184 r8192 d15488 u36864 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 206848 [ 0.000000] Kernel command line: console=ttyAMA2,115200n8 vmalloc=256M root=/dev/mmcblk0p3 rootwait mem=128M@0 mali.mali_mem=32M@128M hwmem=168M@160M mem=48M@328M mem_issw=1M@383M mem=640M@384M [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Memory: 128MB 48MB 640MB = 816MB total [ 0.000000] Memory: 818892k/818892k available, 16692k reserved, 278528K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xef800000 - 0xff000000 ( 248 MB) [ 0.000000] lowmem : 0xc0000000 - 0xef000000 ( 752 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc07c6344 (7929 kB) [ 0.000000] .init : 0xc07c7000 - 0xc0813380 ( 305 kB) [ 0.000000] .data : 0xc0814000 - 0xc087b850 ( 415 kB) [ 0.000000] .bss : 0xc087b874 - 0xc0909028 ( 566 kB) [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] NR_IRQS:670 [ 0.000000] PRCMU firmware: U8500, version 3.4.9 [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] Console: colour dummy device 80x30 [ 0.000457] Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816) [ 0.090026] pid_max: default: 32768 minimum: 301 [ 0.090240] Security Framework initialized [ 0.090332] AppArmor: AppArmor initialized [ 0.090454] Mount-cache hash table entries: 512 [ 0.091888] Initializing cgroup subsys cpuacct [ 0.091979] CPU: Testing write buffer coherency: ok [ 0.092041] ftrace: allocating 20089 entries in 59 pages [ 0.135833] CPU0: thread -1, cpu 0, socket 3, mpidr 80000300 [ 0.135894] smp_twd: clock not found: -2 [ 0.135894] Calibrating local timer... 399.10MHz. [ 0.190032] hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available [ 0.190185] Setting up static identity map for 0x577a68 - 0x577ac0 [ 0.190216] L310 cache controller enabled [ 0.190216] l2x0: 8 ways, CACHE_ID 0x410000c5, AUX_CTRL 0x7e060800, Cache size: 524288 B [ 0.250549] CPU1: Booted secondary processor [ 0.339965] CPU1: thread -1, cpu 1, socket 3, mpidr 80000301 [ 0.340087] Brought up 2 CPUs [ 0.340087] SMP: Total of 2 processors activated (3188.32 BogoMIPS). [ 0.340942] devtmpfs: initialized [ 0.346435] pinctrl core: initialized pinctrl subsystem [ 0.347686] dummy: [ 0.348632] NET: Registered protocol family 16 [ 0.349487] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 0.352569] gpio gpio.0: at address f812e000 [ 0.353149] gpio gpio.1: at address f812e080 [ 0.353729] gpio gpio.2: at address f800e000 [ 0.354309] gpio gpio.3: at address f800e080 [ 0.354858] gpio gpio.4: at address f800e100 [ 0.355438] gpio gpio.5: at address f800e180 [ 0.356018] gpio gpio.6: at address f811e000 [ 0.356597] gpio gpio.7: at address f811e080 [ 0.357177] gpio gpio.8: at address fa3fe000 [ 0.358398] pinctrl-nomadik pinctrl-db8500: initialized Nomadik pin control driver [ 0.360229] ab8500-core ab8500-core.0: detected chip, AB8500 rev. 3.0 [ 0.360290] ab8500-core ab8500-core.0: switch off cause(s) (0x20): [ 0.360290] "Battery level lower than power on reset threshold" [ 0.365112] DB8500 PRCMU initialized [ 0.366302] mop500_msp_init: Register platform-device 'snd-soc-u8500'. [ 0.366485] Initialize MSP I2S-devices. [ 0.366516] Register platform-device 'ux500-msp-i2s', id 0, irq 63 [ 0.366729] Register platform-device 'ux500-msp-i2s', id 1, irq 94 [ 0.366912] Register platform-device 'ux500-msp-i2s', id 2, irq 130 [ 0.367095] Register platform-device 'ux500-msp-i2s', id 3, irq 94 [ 0.367401] mop500_msp_init: Register platform-device 'ux500-pcm' [ 0.368286] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. [ 0.368316] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.368865] db8500-vape: [ 0.369171] db8500-varm: [ 0.369476] db8500-vmodem: [ 0.369750] db8500-vpll: [ 0.370208] db8500-vsmps1: [ 0.370483] db8500-vsmps2: [ 0.370758] db8500-vsmps3: [ 0.371032] db8500-vrf1: [ 0.371307] db8500-sva-mmdsp: [ 0.371582] db8500-sva-mmdsp-ret: [ 0.371856] db8500-sva-pipe: [ 0.372131] db8500-sia-mmdsp: [ 0.372406] db8500-sia-mmdsp-ret: [ 0.372680] db8500-sia-pipe: [ 0.372955] db8500-sga: [ 0.372985] db8500-sga: supplied by db8500-vape [ 0.373291] db8500-b2r2-mcde: [ 0.373321] db8500-b2r2-mcde: supplied by db8500-vape [ 0.373626] db8500-esram12: [ 0.373931] db8500-esram12-ret: [ 0.374206] db8500-esram34: [ 0.374511] db8500-esram34-ret: [ 0.374786] Serial: AMBA PL011 UART driver [ 0.374969] uart0: ttyAMA0 at MMIO 0x80120000 (irq = 43) is a PL011 rev3 [ 0.375396] uart-pl011 uart1: could not get default pinstate [ 0.375427] uart1: ttyAMA1 at MMIO 0x80121000 (irq = 51) is a PL011 rev3 [ 0.375793] uart-pl011 uart2: could not get default pinstate [ 0.375823] uart2: ttyAMA2 at MMIO 0x80007000 (irq = 58) is a PL011 rev3 [ 0.922393] console [ttyAMA2] enabled [ 0.946716] bio: create slab <bio-0> at 0 And this is where the board would lock up. -- Steve
Index: arm-test.git/arch/arm/mach-ux500/Kconfig =================================================================== --- arm-test.git.orig/arch/arm/mach-ux500/Kconfig 2013-01-24 11:29:36.000000000 -0500 +++ arm-test.git/arch/arm/mach-ux500/Kconfig 2013-01-24 11:30:28.574250603 -0500 @@ -8,7 +8,6 @@ config UX500_SOC_COMMON select ARM_GIC select CACHE_L2X0 select CLKSRC_NOMADIK_MTU - select COMMON_CLK select PINCTRL select PINCTRL_NOMADIK select PL310_ERRATA_753970 if CACHE_PL310 Index: arm-test.git/arch/arm/mach-ux500/Makefile =================================================================== --- arm-test.git.orig/arch/arm/mach-ux500/Makefile 2013-01-24 10:33:45.000000000 -0500 +++ arm-test.git/arch/arm/mach-ux500/Makefile 2013-01-24 11:30:19.402046175 -0500 @@ -2,7 +2,7 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := cpu.o devices.o devices-common.o \ +obj-y := clock.o cpu.o devices.o devices-common.o \ id.o usb.o timer.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o Index: arm-test.git/arch/arm/mach-ux500/clock.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ arm-test.git/arch/arm/mach-ux500/clock.c 2013-01-24 11:52:41.083970656 -0500 @@ -0,0 +1,715 @@ +/* + * Copyright (C) 2009 ST-Ericsson + * Copyright (C) 2009 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/cpufreq.h> + +//#include <plat/mtu.h> +#include <mach/hardware.h> +#include "clock.h" + +#ifdef CONFIG_DEBUG_FS +#include <linux/debugfs.h> +#include <linux/uaccess.h> /* for copy_from_user */ +static LIST_HEAD(clk_list); +#endif + +#define PRCC_PCKEN 0x00 +#define PRCC_PCKDIS 0x04 +#define PRCC_KCKEN 0x08 +#define PRCC_KCKDIS 0x0C + +#define PRCM_YYCLKEN0_MGT_SET 0x510 +#define PRCM_YYCLKEN1_MGT_SET 0x514 +#define PRCM_YYCLKEN0_MGT_CLR 0x518 +#define PRCM_YYCLKEN1_MGT_CLR 0x51C +#define PRCM_YYCLKEN0_MGT_VAL 0x520 +#define PRCM_YYCLKEN1_MGT_VAL 0x524 + +#define PRCM_SVAMMDSPCLK_MGT 0x008 +#define PRCM_SIAMMDSPCLK_MGT 0x00C +#define PRCM_SGACLK_MGT 0x014 +#define PRCM_UARTCLK_MGT 0x018 +#define PRCM_MSP02CLK_MGT 0x01C +#define PRCM_MSP1CLK_MGT 0x288 +#define PRCM_I2CCLK_MGT 0x020 +#define PRCM_SDMMCCLK_MGT 0x024 +#define PRCM_SLIMCLK_MGT 0x028 +#define PRCM_PER1CLK_MGT 0x02C +#define PRCM_PER2CLK_MGT 0x030 +#define PRCM_PER3CLK_MGT 0x034 +#define PRCM_PER5CLK_MGT 0x038 +#define PRCM_PER6CLK_MGT 0x03C +#define PRCM_PER7CLK_MGT 0x040 +#define PRCM_LCDCLK_MGT 0x044 +#define PRCM_BMLCLK_MGT 0x04C +#define PRCM_HSITXCLK_MGT 0x050 +#define PRCM_HSIRXCLK_MGT 0x054 +#define PRCM_HDMICLK_MGT 0x058 +#define PRCM_APEATCLK_MGT 0x05C +#define PRCM_APETRACECLK_MGT 0x060 +#define PRCM_MCDECLK_MGT 0x064 +#define PRCM_IPI2CCLK_MGT 0x068 +#define PRCM_DSIALTCLK_MGT 0x06C +#define PRCM_DMACLK_MGT 0x074 +#define PRCM_B2R2CLK_MGT 0x078 +#define PRCM_TVCLK_MGT 0x07C +#define PRCM_TCR 0x1C8 +#define PRCM_TCR_STOPPED (1 << 16) +#define PRCM_TCR_DOZE_MODE (1 << 17) +#define PRCM_UNIPROCLK_MGT 0x278 +#define PRCM_SSPCLK_MGT 0x280 +#define PRCM_RNGCLK_MGT 0x284 +#define PRCM_UICCCLK_MGT 0x27C + +#define PRCM_MGT_ENABLE (1 << 8) + +static DEFINE_SPINLOCK(clocks_lock); + +static void __clk_enable(struct clk *clk) +{ + if (clk->enabled++ == 0) { + if (clk->parent_cluster) + __clk_enable(clk->parent_cluster); + + if (clk->parent_periph) + __clk_enable(clk->parent_periph); + + if (clk->ops && clk->ops->enable) + clk->ops->enable(clk); + } +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + __clk_enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + + return 0; +} +EXPORT_SYMBOL(clk_enable); + +static void __clk_disable(struct clk *clk) +{ + if (--clk->enabled == 0) { + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + + if (clk->parent_periph) + __clk_disable(clk->parent_periph); + + if (clk->parent_cluster) + __clk_disable(clk->parent_cluster); + } +} + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + WARN_ON(!clk->enabled); + + spin_lock_irqsave(&clocks_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +/* + * The MTU has a separate, rather complex muxing setup + * with alternative parents (peripheral cluster or + * ULP or fixed 32768 Hz) depending on settings + */ +static unsigned long clk_mtu_get_rate(struct clk *clk) +{ + void __iomem *addr; + u32 tcr; + int mtu = (int) clk->data; + /* + * One of these is selected eventually + * TODO: Replace the constant with a reference + * to the ULP source once this is modeled. + */ + unsigned long clk32k = 32768; + unsigned long mturate; + unsigned long retclk; + + if (cpu_is_u8500_family()) + addr = __io_address(U8500_PRCMU_BASE); + else + ux500_unknown_soc(); + + /* + * On a startup, always conifgure the TCR to the doze mode; + * bootloaders do it for us. Do this in the kernel too. + */ + writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); + + tcr = readl(addr + PRCM_TCR); + + /* Get the rate from the parent as a default */ + if (clk->parent_periph) + mturate = clk_get_rate(clk->parent_periph); + else if (clk->parent_cluster) + mturate = clk_get_rate(clk->parent_cluster); + else + /* We need to be connected SOMEWHERE */ + BUG(); + + /* Return the clock selected for this MTU */ + if (tcr & (1 << mtu)) + retclk = clk32k; + else + retclk = mturate; + + pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); + return retclk; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long rate; + + /* + * If there is a custom getrate callback for this clock, + * it will take precedence. + */ + if (clk->get_rate) + return clk->get_rate(clk); + + if (clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + rate = clk->rate; + if (!rate) { + if (clk->parent_periph) + rate = clk_get_rate(clk->parent_periph); + else if (clk->parent_cluster) + rate = clk_get_rate(clk->parent_cluster); + } + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + /*TODO*/ + return rate; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + clk->rate = rate; + return 0; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + /*TODO*/ + return -ENOSYS; +} +EXPORT_SYMBOL(clk_set_parent); + +static void clk_prcmu_enable(struct clk *clk) +{ + void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) + + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_set_reg); +} + +static void clk_prcmu_disable(struct clk *clk) +{ + void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) + + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; + + writel(1 << clk->prcmu_cg_bit, cg_clr_reg); +} + +static struct clkops clk_prcmu_ops = { + .enable = clk_prcmu_enable, + .disable = clk_prcmu_disable, +}; + +static unsigned int clkrst_base[] = { + [1] = U8500_CLKRST1_BASE, + [2] = U8500_CLKRST2_BASE, + [3] = U8500_CLKRST3_BASE, + [5] = U8500_CLKRST5_BASE, + [6] = U8500_CLKRST6_BASE, +}; + +static void clk_prcc_enable(struct clk *clk) +{ + void __iomem *addr = __io_address(clkrst_base[clk->cluster]); + + if (clk->prcc_kernel != -1) + writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); + + if (clk->prcc_bus != -1) + writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); +} + +static void clk_prcc_disable(struct clk *clk) +{ + void __iomem *addr = __io_address(clkrst_base[clk->cluster]); + + if (clk->prcc_bus != -1) + writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); + + if (clk->prcc_kernel != -1) + writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); +} + +static struct clkops clk_prcc_ops = { + .enable = clk_prcc_enable, + .disable = clk_prcc_disable, +}; + +static struct clk clk_32khz = { + .name = "clk_32khz", + .rate = 32000, +}; + +/* + * PRCMU level clock gating + */ + +/* Bank 0 */ +static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); +static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); +static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); +static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); +static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); +static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ +static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); +static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000); +static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); +static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); +static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); +static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); +static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); +static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); +static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); +static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); +static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); +static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); +static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); +static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); +static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); +static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); +static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); +static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ +static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); +static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); +static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); +static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ +static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ + +/* Bank 1 */ +static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ +static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ + +/* + * PRCC level clock gating + * Format: per#, clk, PCKEN bit, KCKEN bit, parent + */ + +/* Peripheral Cluster #1 */ +static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); +static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); +static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL); +static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk); +static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); +static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); +static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); + +/* Peripheral Cluster #2 */ +static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL); +static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL); +static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL); +static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL); +static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk); +static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL); +static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL); +static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL); +static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk); + +/* Peripheral Cluster #3 */ +static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); +static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); +static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); +static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); +static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); +static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk); +static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk); +static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); + +/* Peripheral Cluster #4 is in the always on domain */ + +/* Peripheral Cluster #5 */ +static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); +static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); + +/* Peripheral Cluster #6 */ + +/* MTU ID in data */ +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0); +static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL); +static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk); +static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL); +static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); + +static struct clk clk_dummy_apb_pclk = { + .name = "apb_pclk", +}; + +static struct clk_lookup u8500_clks[] = { + CLK(dummy_apb_pclk, NULL, "apb_pclk"), + + /* Peripheral Cluster #1 */ + CLK(gpio0, "gpio.0", NULL), + CLK(gpio0, "gpio.1", NULL), + CLK(slimbus0, "slimbus0", NULL), + CLK(i2c2, "nmk-i2c.2", NULL), + CLK(sdi0, "sdi0", NULL), + CLK(msp0, "ux500-msp-i2s.0", NULL), + CLK(i2c1, "nmk-i2c.1", NULL), + CLK(uart1, "uart1", NULL), + CLK(uart0, "uart0", NULL), + + /* Peripheral Cluster #3 */ + CLK(gpio2, "gpio.2", NULL), + CLK(gpio2, "gpio.3", NULL), + CLK(gpio2, "gpio.4", NULL), + CLK(gpio2, "gpio.5", NULL), + CLK(sdi5, "sdi5", NULL), + CLK(uart2, "uart2", NULL), + CLK(ske, "ske", NULL), + CLK(ske, "nmk-ske-keypad", NULL), + CLK(sdi2, "sdi2", NULL), + CLK(i2c0, "nmk-i2c.0", NULL), + CLK(fsmc, "fsmc", NULL), + + /* Peripheral Cluster #5 */ + CLK(gpio3, "gpio.8", NULL), + + /* Peripheral Cluster #6 */ + CLK(hash1, "hash1", NULL), + CLK(pka, "pka", NULL), + CLK(hash0, "hash0", NULL), + CLK(cryp0, "cryp0", NULL), + CLK(cryp1, "cryp1", NULL), + + /* PRCMU level clock gating */ + + /* Bank 0 */ + CLK(svaclk, "sva", NULL), + CLK(siaclk, "sia", NULL), + CLK(sgaclk, "sga", NULL), + CLK(slimclk, "slim", NULL), + CLK(lcdclk, "lcd", NULL), + CLK(bmlclk, "bml", NULL), + CLK(hsitxclk, "stm-hsi.0", NULL), + CLK(hsirxclk, "stm-hsi.1", NULL), + CLK(hdmiclk, "hdmi", NULL), + CLK(apeatclk, "apeat", NULL), + CLK(apetraceclk, "apetrace", NULL), + CLK(mcdeclk, "mcde", NULL), + CLK(ipi2clk, "ipi2", NULL), + CLK(dmaclk, "dma40.0", NULL), + CLK(b2r2clk, "b2r2", NULL), + CLK(tvclk, "tv", NULL), + + /* Peripheral Cluster #1 */ + CLK(i2c4, "nmk-i2c.4", NULL), + CLK(spi3, "spi3", NULL), + CLK(msp1, "ux500-msp-i2s.1", NULL), + CLK(msp3, "ux500-msp-i2s.3", NULL), + + /* Peripheral Cluster #2 */ + CLK(gpio1, "gpio.6", NULL), + CLK(gpio1, "gpio.7", NULL), + CLK(ssitx, "ssitx", NULL), + CLK(ssirx, "ssirx", NULL), + CLK(spi0, "spi0", NULL), + CLK(sdi3, "sdi3", NULL), + CLK(sdi1, "sdi1", NULL), + CLK(msp2, "ux500-msp-i2s.2", NULL), + CLK(sdi4, "sdi4", NULL), + CLK(pwl, "pwl", NULL), + CLK(spi1, "spi1", NULL), + CLK(spi2, "spi2", NULL), + CLK(i2c3, "nmk-i2c.3", NULL), + + /* Peripheral Cluster #3 */ + CLK(ssp1, "ssp1", NULL), + CLK(ssp0, "ssp0", NULL), + + /* Peripheral Cluster #5 */ + CLK(usb, "musb-ux500.0", "usb"), + + /* Peripheral Cluster #6 */ + CLK(mtu1, "mtu1", NULL), + CLK(mtu0, "mtu0", NULL), + CLK(cfgreg, "cfgreg", NULL), + CLK(hash1, "hash1", NULL), + CLK(unipro, "unipro", NULL), + CLK(rng, "rng", NULL), + + /* PRCMU level clock gating */ + + /* Bank 0 */ + CLK(uniproclk, "uniproclk", NULL), + CLK(dsialtclk, "dsialt", NULL), + + /* Bank 1 */ + CLK(rngclk, "rng", NULL), + CLK(uiccclk, "uicc", NULL), +}; + +#ifdef CONFIG_DEBUG_FS +/* + * debugfs support to trace clock tree hierarchy and attributes with + * powerdebug + */ +static struct dentry *clk_debugfs_root; + +void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) +{ + while (num--) { + /* Check that the clock has not been already registered */ + if (!(cl->clk->list.prev != cl->clk->list.next)) + list_add_tail(&cl->clk->list, &clk_list); + + cl++; + } +} + +static ssize_t usecount_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) +{ + struct clk *clk = file->f_dentry->d_inode->i_private; + char cusecount[128]; + unsigned int len; + + len = sprintf(cusecount, "%u\n", clk->enabled); + return simple_read_from_buffer(buf, size, off, cusecount, len); +} + +static ssize_t rate_dbg_read(struct file *file, char __user *buf, + size_t size, loff_t *off) +{ + struct clk *clk = file->f_dentry->d_inode->i_private; + char crate[128]; + unsigned int rate; + unsigned int len; + + rate = clk_get_rate(clk); + len = sprintf(crate, "%u\n", rate); + return simple_read_from_buffer(buf, size, off, crate, len); +} + +static const struct file_operations usecount_fops = { + .read = usecount_dbg_read, +}; + +static const struct file_operations set_rate_fops = { + .read = rate_dbg_read, +}; + +static struct dentry *clk_debugfs_register_dir(struct clk *c, + struct dentry *p_dentry) +{ + struct dentry *d, *clk_d; + const char *p = c->name; + + if (!p) + p = "BUG"; + + clk_d = debugfs_create_dir(p, p_dentry); + if (!clk_d) + return NULL; + + d = debugfs_create_file("usecount", S_IRUGO, + clk_d, c, &usecount_fops); + if (!d) + goto err_out; + d = debugfs_create_file("rate", S_IRUGO, + clk_d, c, &set_rate_fops); + if (!d) + goto err_out; + /* + * TODO : not currently available in ux500 + * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); + * if (!d) + * goto err_out; + */ + + return clk_d; + +err_out: + debugfs_remove_recursive(clk_d); + return NULL; +} + +static int clk_debugfs_register_one(struct clk *c) +{ + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (!(bpa && !pa)) { + c->dent = clk_debugfs_register_dir(c, + pa ? pa->dent : clk_debugfs_root); + if (!c->dent) + return -ENOMEM; + } + + if (bpa) { + c->dent_bus = clk_debugfs_register_dir(c, + bpa->dent_bus ? bpa->dent_bus : bpa->dent); + if ((!c->dent_bus) && (c->dent)) { + debugfs_remove_recursive(c->dent); + c->dent = NULL; + return -ENOMEM; + } + } + return 0; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->parent_periph; + struct clk *bpa = c->parent_cluster; + + if (pa && (!pa->dent && !pa->dent_bus)) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (bpa && (!bpa->dent && !bpa->dent_bus)) { + err = clk_debugfs_register(bpa); + if (err) + return err; + } + + if ((!c->dent) && (!c->dent_bus)) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clk_list, list) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} + +#endif /* defined(CONFIG_DEBUG_FS) */ + +unsigned long clk_smp_twd_rate = 500000000; + +unsigned long clk_smp_twd_get_rate(struct clk *clk) +{ + return clk_smp_twd_rate; +} + +static struct clk clk_smp_twd = { + .get_rate = clk_smp_twd_get_rate, + .name = "smp_twd", +}; + +static struct clk_lookup clk_smp_twd_lookup = { + .dev_id = "smp_twd", + .clk = &clk_smp_twd, +}; + +#ifdef CONFIG_CPU_FREQ + +static int clk_twd_cpufreq_transition(struct notifier_block *nb, + unsigned long state, void *data) +{ + struct cpufreq_freqs *f = data; + + if (state == CPUFREQ_PRECHANGE) { + /* Save frequency in simple Hz */ + clk_smp_twd_rate = (f->new * 1000) / 2; + } + + return NOTIFY_OK; +} + +static struct notifier_block clk_twd_cpufreq_nb = { + .notifier_call = clk_twd_cpufreq_transition, +}; + +int clk_init_smp_twd_cpufreq(void) +{ + return cpufreq_register_notifier(&clk_twd_cpufreq_nb, + CPUFREQ_TRANSITION_NOTIFIER); +} + +#endif + +int __init clk_init(void) +{ + clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); + clkdev_add(&clk_smp_twd_lookup); + +#ifdef CONFIG_DEBUG_FS + clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); +#endif + return 0; +} Index: arm-test.git/arch/arm/mach-ux500/clock.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ arm-test.git/arch/arm/mach-ux500/clock.h 2013-01-24 11:30:19.402046175 -0500 @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2010 ST-Ericsson + * Copyright (C) 2009 STMicroelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * struct clkops - ux500 clock operations + * @enable: function to enable the clock + * @disable: function to disable the clock + * @get_rate: function to get the current clock rate + * + * This structure contains function pointers to functions that will be used to + * control the clock. All of these functions are optional. If get_rate is + * NULL, the rate in the struct clk will be used. + */ +struct clkops { + void (*enable) (struct clk *); + void (*disable) (struct clk *); + unsigned long (*get_rate) (struct clk *); + int (*set_parent)(struct clk *, struct clk *); +}; + +/** + * struct clk - ux500 clock structure + * @ops: pointer to clkops struct used to control this clock + * @name: name, for debugging + * @enabled: refcount. positive if enabled, zero if disabled + * @get_rate: custom callback for getting the clock rate + * @data: custom per-clock data for example for the get_rate + * callback + * @rate: fixed rate for clocks which don't implement + * ops->getrate + * @prcmu_cg_off: address offset of the combined enable/disable register + * (used on u8500v1) + * @prcmu_cg_bit: bit in the combined enable/disable register (used on + * u8500v1) + * @prcmu_cg_mgt: address of the enable/disable register (used on + * u8500ed) + * @cluster: peripheral cluster number + * @prcc_bus: bit for the bus clock in the peripheral's CLKRST + * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. + * -1 if no kernel clock exists. + * @parent_cluster: pointer to parent's cluster clk struct + * @parent_periph: pointer to parent's peripheral clk struct + * + * Peripherals are organised into clusters, and each cluster has an associated + * bus clock. Some peripherals also have a parent peripheral clock. + * + * In order to enable a clock for a peripheral, we need to enable: + * (1) the parent cluster (bus) clock at the PRCMU level + * (2) the parent peripheral clock (if any) at the PRCMU level + * (3) the peripheral's bus & kernel clock at the PRCC level + * + * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each + * of the cluster and peripheral clocks, and hooking these as the parents of + * the individual peripheral clocks. + * + * (3) is handled by specifying the bits in the PRCC control registers required + * to enable these clocks and modifying them in the ->enable and + * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). + * + * This structure describes both the PRCMU-level clocks and PRCC-level clocks. + * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, + * prcc, and parent pointers are only used for the PRCC-level clocks. + */ +struct clk { + const struct clkops *ops; + const char *name; + unsigned int enabled; + unsigned long (*get_rate)(struct clk *); + void *data; + + unsigned long rate; + struct list_head list; + + /* These three are only for PRCMU clks */ + + unsigned int prcmu_cg_off; + unsigned int prcmu_cg_bit; + unsigned int prcmu_cg_mgt; + + /* The rest are only for PRCC clks */ + + int cluster; + unsigned int prcc_bus; + unsigned int prcc_kernel; + + struct clk *parent_cluster; + struct clk *parent_periph; +#if defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ + struct dentry *dent_bus; /* For visible tree hierarchy */ +#endif +}; + +#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .prcmu_cg_mgt = PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcmu_ops, \ + .prcmu_cg_off = _cg_off, \ + .prcmu_cg_bit = _cg_bit, \ + .rate = _rate, \ + .prcmu_cg_mgt = PRCM_##_reg##_MGT \ + } + +#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcc_ops, \ + .cluster = _pclust, \ + .prcc_bus = _bus_en, \ + .prcc_kernel = _kernel_en, \ + .parent_cluster = &clk_per##_pclust##clk, \ + .parent_periph = _kernclk \ + } + +#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ +struct clk clk_##_name = { \ + .name = #_name, \ + .ops = &clk_prcc_ops, \ + .cluster = _pclust, \ + .prcc_bus = _bus_en, \ + .prcc_kernel = _kernel_en, \ + .parent_cluster = &clk_per##_pclust##clk, \ + .parent_periph = _kernclk, \ + .get_rate = _callback, \ + .data = (void *) _data \ + } + + +#define CLK(_clk, _devname, _conname) \ + { \ + .clk = &clk_##_clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } + +int __init clk_db8500_ed_fixup(void); +int __init clk_init(void); + +#ifdef CONFIG_DEBUG_FS +int clk_debugfs_init(void); +#else +static inline int clk_debugfs_init(void) { return 0; } +#endif + +#ifdef CONFIG_CPU_FREQ +int clk_init_smp_twd_cpufreq(void); +#else +static inline int clk_init_smp_twd_cpufreq(void) { return 0; } +#endif Index: arm-test.git/arch/arm/mach-ux500/cpu.c =================================================================== --- arm-test.git.orig/arch/arm/mach-ux500/cpu.c 2013-01-24 11:26:15.000000000 -0500 +++ arm-test.git/arch/arm/mach-ux500/cpu.c 2013-01-24 11:40:20.547446502 -0500 @@ -8,6 +8,7 @@ #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk.h> #include <linux/mfd/db8500-prcmu.h> #include <linux/clksrc-dbx500-prcmu.h> #include <linux/sys_soc.h> @@ -17,7 +18,6 @@ #include <linux/of.h> #include <linux/of_irq.h> #include <linux/irq.h> -#include <linux/platform_data/clk-ux500.h> #include <asm/hardware/gic.h> #include <asm/mach/map.h> @@ -28,6 +28,8 @@ #include "board-mop500.h" +#include "clock.h" + void __iomem *_PRCMU_BASE; /* @@ -73,18 +75,13 @@ void __init ux500_init_irq(void) */ if (cpu_is_u8500_family()) db8500_prcmu_early_init(); - - if (cpu_is_u8500_family()) - u8500_clk_init(); - else if (cpu_is_u9540()) - u9540_clk_init(); - else if (cpu_is_u8540()) - u8540_clk_init(); + clk_init(); } void __init ux500_init_late(void) { - mop500_uib_init(); + clk_debugfs_init(); + clk_init_smp_twd_cpufreq(); } static const char * __init ux500_get_machine(void) Index: arm-test.git/drivers/clk/Makefile =================================================================== --- arm-test.git.orig/drivers/clk/Makefile 2013-01-24 11:29:36.000000000 -0500 +++ arm-test.git/drivers/clk/Makefile 2013-01-24 11:32:35.297073843 -0500 @@ -18,7 +18,6 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o -obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
I tried to get my snowball board working on the latest kernel, but it locks up hard very early on boot up. I bisected it down to this commit: commit ebc96db7632f987e0b9bffcb782cf5cfb8afb0dd Author: Ulf Hansson <ulf.hansson@linaro.org> Date: Mon Aug 27 15:45:53 2012 +0200 ARM: ux500: Switch to use common clock framework Remove machine specific clock implementation and switch to use new common clock framework. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> I reverted the change (tweaking it to get it to compile again), and sure enough, I'm able to boot the board again. I'm not sure what to do about this, but I wanted to let you know that the common clock framework does not support my snowball board. Below is the changes I made to get the board working on 3.8-rc4. -- Steve --- arch/arm/mach-ux500/Kconfig | 1 arch/arm/mach-ux500/Makefile | 2 arch/arm/mach-ux500/clock.c | 715 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-ux500/clock.h | 164 +++++++++ arch/arm/mach-ux500/cpu.c | 15 drivers/clk/Makefile | 1 6 files changed, 886 insertions(+), 12 deletions(-)