@@ -1,6 +1,7 @@
/*
- * nVidia Tegra device tree board support
+ * NVIDIA Tegra SoC device tree board support
*
+ * Copyright (C) 2011, 2013, NVIDIA Corporation
* Copyright (C) 2010 Secret Lab Technologies, Ltd.
* Copyright (C) 2010 Google, Inc.
*
@@ -67,7 +68,7 @@ static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
.vbus_gpio = -1,
};
-static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+static struct of_dev_auxdata tegra_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0",
&tegra_ehci1_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1",
@@ -84,7 +85,7 @@ static void __init tegra_dt_init(void)
* devices
*/
of_platform_populate(NULL, of_default_bus_match_table,
- tegra20_auxdata_lookup, NULL);
+ tegra_auxdata_lookup, NULL);
}
static void __init trimslice_init(void)
@@ -111,7 +112,8 @@ static void __init harmony_init(void)
static void __init paz00_init(void)
{
- tegra_paz00_wifikill_init();
+ if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+ tegra_paz00_wifikill_init();
}
static struct {
@@ -137,12 +139,14 @@ static void __init tegra_dt_init_late(void)
}
}
-static const char *tegra20_dt_board_compat[] = {
+static const char * const tegra_dt_board_compat[] = {
+ "nvidia,tegra114",
+ "nvidia,tegra30",
"nvidia,tegra20",
NULL
};
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
.map_io = tegra_map_common_io,
.smp = smp_ops(tegra_smp_ops),
.init_early = tegra_init_early,
@@ -151,5 +155,5 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
.init_machine = tegra_dt_init,
.init_late = tegra_dt_init_late,
.restart = tegra_assert_system_reset,
- .dt_compat = tegra20_dt_board_compat,
+ .dt_compat = tegra_dt_board_compat,
MACHINE_END