diff mbox

[1/3] ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone

Message ID 1364196478-16688-2-git-send-email-mugunthanvnm@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mugunthan V N March 25, 2013, 7:27 a.m. UTC 
Add pinmux configurations for MII based CPSW ethernet to am335x-bone.
In this patch, only single named mode/state is added and these pins
are configured during pinctrl driver initialization.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
---
 arch/arm/boot/dts/am335x-bone.dts |   25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

Comments

Jan Lübbe April 1, 2013, 10:45 a.m. UTC | #1 
On Mon, Mar 25, 2013 at 12:57:56PM +0530, Mugunthan V N wrote:
>  	am33xx_pinmux: pinmux@44e10800 {
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&user_leds_s0>;
> +		pinctrl-0 = <&user_leds_s0 &cpsw_s0>;

Why do you add &cpsw_s0 to the pinmux node? This should go into the cpsw
node itself, which should work without further code changes since:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=ab78029ecc347
(drivers/pinctrl: grab default handles from device core)

Same for the other patches.

Regards,
Jan
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 11b240c..f90e665 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -26,7 +26,7 @@ 
 
 	am33xx_pinmux: pinmux@44e10800 {
 		pinctrl-names = "default";
-		pinctrl-0 = <&user_leds_s0>;
+		pinctrl-0 = <&user_leds_s0 &cpsw_s0>;
 
 		user_leds_s0: user_leds_s0 {
 			pinctrl-single,pins = <
@@ -36,6 +36,29 @@ 
 				0x60 0x17	/* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
 			>;
 		};
+
+		cpsw_s0: cpsw_s0 {
+			pinctrl-single,pins = <
+				/* Slave 1 */
+				0x110 0x20	/* mii1_rxerr.mii1_rxerr, MODE0 | INPUT */
+				0x114 0x0	/* mii1_txen.mii1_txen, MODE0 | OUTPUT */
+				0x118 0x20	/* mii1_rxdv.mii1_rxdv, MODE0 | INPUT_PULLDOWN */
+				0x11c 0x0	/* mii1_txd3.mii1_txd3, MODE0 | OUTPUT */
+				0x120 0x0	/* mii1_txd2.mii1_txd2, MODE0 | OUTPUT */
+				0x124 0x0	/* mii1_txd1.mii1_txd1, MODE0 | OUTPUT */
+				0x128 0x0	/* mii1_txd0.mii1_txd0, MODE0 | OUTPUT */
+				0x12c 0x20	/* mii1_txclk.mii1_txclk, MODE0 | INPUT_PULLDOWN */
+				0x130 0x20	/* mii1_rxclk.mii1_rxclk, MODE0 | INPUT_PULLDOWN */
+				0x134 0x20	/* mii1_rxd3.mii1_rxd3, MODE0 | INPUT_PULLDOWN */
+				0x138 0x20	/* mii1_rxd2.mii1_rxd2, MODE0 | INPUT_PULLDOWN */
+				0x13c 0x20	/* mii1_rxd1.mii1_rxd1, MODE0 | INPUT_PULLDOWN */
+				0x140 0x20	/* mii1_rxd0.mii1_rxd0, MODE0 | INPUT_PULLDOWN */
+
+				/* MDIO */
+				0x148 0x30	/* mdio_data.mdio_data, MODE0 | INPUT_PULLUP */
+				0x14c 0x10	/* mdio_clk.mdio_clk, MODE0 | OUTPUT_PULLUP */
+			>;
+		};
 	};
 
 	ocp {