@@ -1,9 +1,15 @@
NVIDIA Tegra Power Management Controller (PMC)
-Properties:
+Required properties:
- name : Should be pmc
- compatible : Should contain "nvidia,tegra<chip>-pmc".
- reg : Offset and length of the register set for the device
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Must include the following entries:
+ "pclk" (The Tegra clock of that name),
+ "clk32k_in" (The 32KHz clock input to Tegra).
+
+Optional properties:
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
The PMU is an external Power Management Unit, whose interrupt output
signal is fed into the PMC. This signal is optionally inverted, and then
@@ -12,8 +18,29 @@ Properties:
Example:
+/ SoC dts including file
pmc@7000f400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car 110>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
nvidia,invert-interrupt;
};
+
+/ Tegra board dts file
+{
+ ...
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+ ...
+};
@@ -839,6 +839,19 @@
status = "okay";
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -18,4 +18,17 @@
pmc {
nvidia,invert-interrupt;
};
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
};
@@ -301,6 +301,8 @@
pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car 261>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
};
iommu {
@@ -447,6 +447,19 @@
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
"nvidia,tegra-audio-wm9712";
@@ -451,6 +451,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
kbc {
status = "okay";
nvidia,debounce-delay-ms = <2>;
@@ -447,6 +447,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -595,6 +595,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -471,6 +471,19 @@
status = "okay";
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
@@ -330,6 +330,19 @@
bus-width = <4>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 191 1>; /* gpio PX7, active low */
@@ -531,6 +531,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -520,6 +520,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
kbc {
status = "okay";
nvidia,debounce-delay-ms = <20>;
@@ -419,6 +419,8 @@
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car 110>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
};
memory-controller@7000f000 {
@@ -268,6 +268,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -322,6 +322,19 @@
bus-width = <8>;
};
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock {
+ compatible = "fixed-clock";
+ reg=<0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -428,6 +428,8 @@
pmc {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
+ clocks = <&tegra_car 218>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
};
memory-controller {
Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- V4: * move the c code to the patch 2/2 of this series * the clock related define should be required properties * fix the oreder of clocks node in DTS file * add Tegra114 support V3: * add clk32k_in as one of the PMC clock source. * add a fixed clock of clk32k_in for Tegra20 & Tegra30 * add binding document for the clock source of PMC * get the clock from DT by of_get_clk_by_name() * fix WARN_ON_ONCE to WARN_ON when there is no clock define in DT V2: * new in this series --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 29 +++++++++++++++++++++- arch/arm/boot/dts/tegra114-dalmore.dts | 13 ++++++++++ arch/arm/boot/dts/tegra114-pluto.dts | 13 ++++++++++ arch/arm/boot/dts/tegra114.dtsi | 2 ++ arch/arm/boot/dts/tegra20-colibri-512.dtsi | 13 ++++++++++ arch/arm/boot/dts/tegra20-harmony.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20-paz00.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20-seaboard.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20-tamonten.dtsi | 13 ++++++++++ arch/arm/boot/dts/tegra20-trimslice.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20-ventana.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20-whistler.dts | 13 ++++++++++ arch/arm/boot/dts/tegra20.dtsi | 2 ++ arch/arm/boot/dts/tegra30-beaver.dts | 13 ++++++++++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 13 ++++++++++ arch/arm/boot/dts/tegra30.dtsi | 2 ++ 16 files changed, 190 insertions(+), 1 deletion(-)