| Message ID | 1366111516-27448-1-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote: > For the device to enter D3 we should enable PCH clock gating. > > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ > 5 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index bddb9a5..e9a82f1 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev) > */ > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) > dev_priv->display.crtc_disable(crtc); > + > + intel_modeset_suspend_hw(dev); > } > > i915_save_state(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index b5a495a..e549e6c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } > > /* modesetting */ > extern void intel_modeset_init_hw(struct drm_device *dev); > +extern void intel_modeset_suspend_hw(struct drm_device *dev); > extern void intel_modeset_init(struct drm_device *dev); > extern void intel_modeset_gem_init(struct drm_device *dev); > extern void intel_modeset_cleanup(struct drm_device *dev); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 457a0a0..e9192bf 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev) > mutex_unlock(&dev->struct_mutex); > } > > +void intel_modeset_suspend_hw(struct drm_device *dev) > +{ > + intel_suspend_hw(dev); > +} > + Why this extra level of indirection? > void intel_modeset_init(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index d7bd031..8b29897 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) > > extern void intel_init_clock_gating(struct drm_device *dev); > +extern void intel_suspend_hw(struct drm_device *dev); > extern void intel_write_eld(struct drm_encoder *encoder, > struct drm_display_mode *mode); > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index baea4fc..3567881 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) > PCH_LP_PARTITION_LEVEL_DISABLE); > } > > +static void lpt_allow_clock_gating(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); > + > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val); > + } So who sets it back when we resume? > +} > + > static void haswell_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev) > dev_priv->display.init_clock_gating(dev); > } > > +void intel_suspend_hw(struct drm_device *dev) > +{ > + if (IS_HASWELL(dev)) > + lpt_allow_clock_gating(dev); Do you need the HSW check? Isn't the LPT LP check enough? > +} > + > void intel_set_power_well(struct drm_device *dev, bool enable) > { > struct drm_i915_private *dev_priv = dev->dev_private; > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote: > On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote: > > For the device to enter D3 we should enable PCH clock gating. > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > > drivers/gpu/drm/i915/intel_drv.h | 1 + > > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ > > 5 files changed, 27 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > > index bddb9a5..e9a82f1 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.c > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev) > > */ > > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) > > dev_priv->display.crtc_disable(crtc); > > + > > + intel_modeset_suspend_hw(dev); > > } > > > > i915_save_state(dev); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index b5a495a..e549e6c 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } > > > > /* modesetting */ > > extern void intel_modeset_init_hw(struct drm_device *dev); > > +extern void intel_modeset_suspend_hw(struct drm_device *dev); > > extern void intel_modeset_init(struct drm_device *dev); > > extern void intel_modeset_gem_init(struct drm_device *dev); > > extern void intel_modeset_cleanup(struct drm_device *dev); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 457a0a0..e9192bf 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev) > > mutex_unlock(&dev->struct_mutex); > > } > > > > +void intel_modeset_suspend_hw(struct drm_device *dev) > > +{ > > + intel_suspend_hw(dev); > > +} > > + > > Why this extra level of indirection? I thought it'd be more symmetric w.r.t. __i915_drm_thaw->intel_modeset_init_hw(). > > void intel_modeset_init(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index d7bd031..8b29897 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, > > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) > > > > extern void intel_init_clock_gating(struct drm_device *dev); > > +extern void intel_suspend_hw(struct drm_device *dev); > > extern void intel_write_eld(struct drm_encoder *encoder, > > struct drm_display_mode *mode); > > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index baea4fc..3567881 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) > > PCH_LP_PARTITION_LEVEL_DISABLE); > > } > > > > +static void lpt_allow_clock_gating(struct drm_device *dev) > > +{ > > + struct drm_i915_private *dev_priv = dev->dev_private; > > + > > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { > > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); > > + > > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; > > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val); > > + } > > So who sets it back when we resume? intel_modeset_init_hw()->intel_init_clock_gating() > > > +} > > + > > static void haswell_init_clock_gating(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev) > > dev_priv->display.init_clock_gating(dev); > > } > > > > +void intel_suspend_hw(struct drm_device *dev) > > +{ > > + if (IS_HASWELL(dev)) > > + lpt_allow_clock_gating(dev); > > Do you need the HSW check? Isn't the LPT LP check enough? Not sure. According to the spec this is a workaround for HSW/LPT. > > +} > > + > > void intel_set_power_well(struct drm_device *dev, bool enable) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > -- > > 1.7.10.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
2013/4/16 Imre Deak <imre.deak@intel.com>: > On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote: >> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote: >> > For the device to enter D3 we should enable PCH clock gating. >> > >> > Signed-off-by: Imre Deak <imre.deak@intel.com> >> > --- >> > drivers/gpu/drm/i915/i915_drv.c | 2 ++ >> > drivers/gpu/drm/i915/i915_drv.h | 1 + >> > drivers/gpu/drm/i915/intel_display.c | 5 +++++ >> > drivers/gpu/drm/i915/intel_drv.h | 1 + >> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ >> > 5 files changed, 27 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> > index bddb9a5..e9a82f1 100644 >> > --- a/drivers/gpu/drm/i915/i915_drv.c >> > +++ b/drivers/gpu/drm/i915/i915_drv.c >> > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev) >> > */ >> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) >> > dev_priv->display.crtc_disable(crtc); >> > + >> > + intel_modeset_suspend_hw(dev); >> > } >> > >> > i915_save_state(dev); >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> > index b5a495a..e549e6c 100644 >> > --- a/drivers/gpu/drm/i915/i915_drv.h >> > +++ b/drivers/gpu/drm/i915/i915_drv.h >> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } >> > >> > /* modesetting */ >> > extern void intel_modeset_init_hw(struct drm_device *dev); >> > +extern void intel_modeset_suspend_hw(struct drm_device *dev); >> > extern void intel_modeset_init(struct drm_device *dev); >> > extern void intel_modeset_gem_init(struct drm_device *dev); >> > extern void intel_modeset_cleanup(struct drm_device *dev); >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> > index 457a0a0..e9192bf 100644 >> > --- a/drivers/gpu/drm/i915/intel_display.c >> > +++ b/drivers/gpu/drm/i915/intel_display.c >> > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev) >> > mutex_unlock(&dev->struct_mutex); >> > } >> > >> > +void intel_modeset_suspend_hw(struct drm_device *dev) >> > +{ >> > + intel_suspend_hw(dev); >> > +} >> > + >> >> Why this extra level of indirection? > > I thought it'd be more symmetric w.r.t. > > __i915_drm_thaw->intel_modeset_init_hw(). > >> > void intel_modeset_init(struct drm_device *dev) >> > { >> > struct drm_i915_private *dev_priv = dev->dev_private; >> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> > index d7bd031..8b29897 100644 >> > --- a/drivers/gpu/drm/i915/intel_drv.h >> > +++ b/drivers/gpu/drm/i915/intel_drv.h >> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, >> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) >> > >> > extern void intel_init_clock_gating(struct drm_device *dev); >> > +extern void intel_suspend_hw(struct drm_device *dev); >> > extern void intel_write_eld(struct drm_encoder *encoder, >> > struct drm_display_mode *mode); >> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> > index baea4fc..3567881 100644 >> > --- a/drivers/gpu/drm/i915/intel_pm.c >> > +++ b/drivers/gpu/drm/i915/intel_pm.c >> > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) >> > PCH_LP_PARTITION_LEVEL_DISABLE); >> > } >> > >> > +static void lpt_allow_clock_gating(struct drm_device *dev) >> > +{ >> > + struct drm_i915_private *dev_priv = dev->dev_private; >> > + >> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { >> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); >> > + >> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; >> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val); >> > + } >> >> So who sets it back when we resume? > > intel_modeset_init_hw()->intel_init_clock_gating() > >> >> > +} >> > + >> > static void haswell_init_clock_gating(struct drm_device *dev) >> > { >> > struct drm_i915_private *dev_priv = dev->dev_private; >> > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev) >> > dev_priv->display.init_clock_gating(dev); >> > } >> > >> > +void intel_suspend_hw(struct drm_device *dev) >> > +{ >> > + if (IS_HASWELL(dev)) >> > + lpt_allow_clock_gating(dev); >> >> Do you need the HSW check? Isn't the LPT LP check enough? > > Not sure. According to the spec this is a workaround for HSW/LPT. I'd check for HAS_PCH_LPT before calling lpt_allow_clock_gating. Let's not forget that, for example, PPT is considered the same as CPT, so any code that's inside a "HAS_PCH_CPT" runs for both SNB and IVB. Optional bikeshed: maybe rename "lpt_allow_clock_gating" to "lpt_suspend_hw"? > >> > +} >> > + >> > void intel_set_power_well(struct drm_device *dev, bool enable) >> > { >> > struct drm_i915_private *dev_priv = dev->dev_private; >> > -- >> > 1.7.10.4 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
On Tue, 2013-04-16 at 14:50 -0300, Paulo Zanoni wrote: > 2013/4/16 Imre Deak <imre.deak@intel.com>: > > On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote: > >> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote: > >> > For the device to enter D3 we should enable PCH clock gating. > >> > > >> > Signed-off-by: Imre Deak <imre.deak@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > >> > drivers/gpu/drm/i915/i915_drv.h | 1 + > >> > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > >> > drivers/gpu/drm/i915/intel_drv.h | 1 + > >> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ > >> > 5 files changed, 27 insertions(+) > >> > > >> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > >> > index bddb9a5..e9a82f1 100644 > >> > --- a/drivers/gpu/drm/i915/i915_drv.c > >> > +++ b/drivers/gpu/drm/i915/i915_drv.c > >> > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev) > >> > */ > >> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) > >> > dev_priv->display.crtc_disable(crtc); > >> > + > >> > + intel_modeset_suspend_hw(dev); > >> > } > >> > > >> > i915_save_state(dev); > >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> > index b5a495a..e549e6c 100644 > >> > --- a/drivers/gpu/drm/i915/i915_drv.h > >> > +++ b/drivers/gpu/drm/i915/i915_drv.h > >> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } > >> > > >> > /* modesetting */ > >> > extern void intel_modeset_init_hw(struct drm_device *dev); > >> > +extern void intel_modeset_suspend_hw(struct drm_device *dev); > >> > extern void intel_modeset_init(struct drm_device *dev); > >> > extern void intel_modeset_gem_init(struct drm_device *dev); > >> > extern void intel_modeset_cleanup(struct drm_device *dev); > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >> > index 457a0a0..e9192bf 100644 > >> > --- a/drivers/gpu/drm/i915/intel_display.c > >> > +++ b/drivers/gpu/drm/i915/intel_display.c > >> > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev) > >> > mutex_unlock(&dev->struct_mutex); > >> > } > >> > > >> > +void intel_modeset_suspend_hw(struct drm_device *dev) > >> > +{ > >> > + intel_suspend_hw(dev); > >> > +} > >> > + > >> > >> Why this extra level of indirection? > > > > I thought it'd be more symmetric w.r.t. > > > > __i915_drm_thaw->intel_modeset_init_hw(). > > > >> > void intel_modeset_init(struct drm_device *dev) > >> > { > >> > struct drm_i915_private *dev_priv = dev->dev_private; > >> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >> > index d7bd031..8b29897 100644 > >> > --- a/drivers/gpu/drm/i915/intel_drv.h > >> > +++ b/drivers/gpu/drm/i915/intel_drv.h > >> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, > >> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) > >> > > >> > extern void intel_init_clock_gating(struct drm_device *dev); > >> > +extern void intel_suspend_hw(struct drm_device *dev); > >> > extern void intel_write_eld(struct drm_encoder *encoder, > >> > struct drm_display_mode *mode); > >> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >> > index baea4fc..3567881 100644 > >> > --- a/drivers/gpu/drm/i915/intel_pm.c > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c > >> > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) > >> > PCH_LP_PARTITION_LEVEL_DISABLE); > >> > } > >> > > >> > +static void lpt_allow_clock_gating(struct drm_device *dev) > >> > +{ > >> > + struct drm_i915_private *dev_priv = dev->dev_private; > >> > + > >> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { > >> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); > >> > + > >> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; > >> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val); > >> > + } > >> > >> So who sets it back when we resume? > > > > intel_modeset_init_hw()->intel_init_clock_gating() > > > >> > >> > +} > >> > + > >> > static void haswell_init_clock_gating(struct drm_device *dev) > >> > { > >> > struct drm_i915_private *dev_priv = dev->dev_private; > >> > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev) > >> > dev_priv->display.init_clock_gating(dev); > >> > } > >> > > >> > +void intel_suspend_hw(struct drm_device *dev) > >> > +{ > >> > + if (IS_HASWELL(dev)) > >> > + lpt_allow_clock_gating(dev); > >> > >> Do you need the HSW check? Isn't the LPT LP check enough? > > > > Not sure. According to the spec this is a workaround for HSW/LPT. > > I'd check for HAS_PCH_LPT before calling lpt_allow_clock_gating. Let's > not forget that, for example, PPT is considered the same as CPT, so > any code that's inside a "HAS_PCH_CPT" runs for both SNB and IVB. > > Optional bikeshed: maybe rename "lpt_allow_clock_gating" to "lpt_suspend_hw"? Ok, will change these. --Imre
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index bddb9a5..e9a82f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev) */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) dev_priv->display.crtc_disable(crtc); + + intel_modeset_suspend_hw(dev); } i915_save_state(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b5a495a..e549e6c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } /* modesetting */ extern void intel_modeset_init_hw(struct drm_device *dev); +extern void intel_modeset_suspend_hw(struct drm_device *dev); extern void intel_modeset_init(struct drm_device *dev); extern void intel_modeset_gem_init(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 457a0a0..e9192bf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev) mutex_unlock(&dev->struct_mutex); } +void intel_modeset_suspend_hw(struct drm_device *dev) +{ + intel_suspend_hw(dev); +} + void intel_modeset_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d7bd031..8b29897 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) extern void intel_init_clock_gating(struct drm_device *dev); +extern void intel_suspend_hw(struct drm_device *dev); extern void intel_write_eld(struct drm_encoder *encoder, struct drm_display_mode *mode); extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index baea4fc..3567881 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) PCH_LP_PARTITION_LEVEL_DISABLE); } +static void lpt_allow_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); + + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; + I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + } +} + static void haswell_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev) dev_priv->display.init_clock_gating(dev); } +void intel_suspend_hw(struct drm_device *dev) +{ + if (IS_HASWELL(dev)) + lpt_allow_clock_gating(dev); +} + void intel_set_power_well(struct drm_device *dev, bool enable) { struct drm_i915_private *dev_priv = dev->dev_private;
For the device to enter D3 we should enable PCH clock gating. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_display.c | 5 +++++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 5 files changed, 27 insertions(+)