| Message ID | 1368939152-11406-8-git-send-email-jun.nakajima@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Il 19/05/2013 06:52, Jun Nakajima ha scritto: > From: Nadav Har'El <nyh@il.ibm.com> > > Some additional comments to preexisting code: > Explain who (L0 or L1) handles EPT violation and misconfiguration exits. > Don't mention "shadow on either EPT or shadow" as the only two options. > > Signed-off-by: Nadav Har'El <nyh@il.ibm.com> > Signed-off-by: Jun Nakajima <jun.nakajima@intel.com> > Signed-off-by: Xinhao Xu <xinhao.xu@intel.com> > --- > arch/x86/kvm/vmx.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c > index b79efd4..4661a22 100644 > --- a/arch/x86/kvm/vmx.c > +++ b/arch/x86/kvm/vmx.c > @@ -6540,7 +6540,20 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) > return nested_cpu_has2(vmcs12, > SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); > case EXIT_REASON_EPT_VIOLATION: > + /* > + * L0 always deals with the EPT violation. If nested EPT is > + * used, and the nested mmu code discovers that the address is > + * missing in the guest EPT table (EPT12), the EPT violation > + * will be injected with nested_ept_inject_page_fault() > + */ > + return 0; > case EXIT_REASON_EPT_MISCONFIG: > + /* > + * L2 never uses directly L1's EPT, but rather L0's own EPT > + * table (shadow on EPT) or a merged EPT table that L0 built > + * (EPT on EPT). So any problems with the structure of the > + * table is L0's fault. > + */ > return 0; > case EXIT_REASON_PREEMPTION_TIMER: > return vmcs12->pin_based_vm_exec_control & > Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index b79efd4..4661a22 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -6540,7 +6540,20 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); case EXIT_REASON_EPT_VIOLATION: + /* + * L0 always deals with the EPT violation. If nested EPT is + * used, and the nested mmu code discovers that the address is + * missing in the guest EPT table (EPT12), the EPT violation + * will be injected with nested_ept_inject_page_fault() + */ + return 0; case EXIT_REASON_EPT_MISCONFIG: + /* + * L2 never uses directly L1's EPT, but rather L0's own EPT + * table (shadow on EPT) or a merged EPT table that L0 built + * (EPT on EPT). So any problems with the structure of the + * table is L0's fault. + */ return 0; case EXIT_REASON_PREEMPTION_TIMER: return vmcs12->pin_based_vm_exec_control &