@@ -87,6 +87,8 @@ config CLK_PPC_CORENET
This adds the clock driver support for Freescale PowerPC corenet
platforms using common clock framework.
+source "drivers/clk/tegra/Kconfig"
+
endmenu
source "drivers/clk/mvebu/Kconfig"
@@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
-obj-$(CONFIG_ARCH_TEGRA) += tegra/
+obj-$(CONFIG_CLK_TEGRA) += tegra/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
obj-$(CONFIG_X86) += x86/
new file mode 100644
@@ -0,0 +1,24 @@
+config CLK_TEGRA
+ bool "Clock driver for NVIDIA Tegra SoCs"
+ depends on ARCH_TEGRA
+ default y
+ help
+ Say y here to enable clock driver support for NVIDIA Tegra SoCs.
+
+ This option provides core functionality; enable support for specific
+ individual SoCs using the options below.
+
+config CLK_TEGRA20
+ bool "Tegra20 clock support"
+ depends on CLK_TEGRA
+ default y
+
+config CLK_TEGRA30
+ bool "Tegra30 clock support"
+ depends on CLK_TEGRA
+ default y
+
+config CLK_TEGRA114
+ bool "Tegra114 clock support"
+ depends on CLK_TEGRA
+ default y
@@ -7,6 +7,6 @@ obj-y += clk-pll.o
obj-y += clk-pll-out.o
obj-y += clk-super.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
+obj-$(CONFIG_CLK_TEGRA20) += clk-tegra20.o
+obj-$(CONFIG_CLK_TEGRA30) += clk-tegra30.o
+obj-$(CONFIG_CLK_TEGRA114) += clk-tegra114.o
@@ -744,7 +744,7 @@ const struct clk_ops tegra_clk_plle_ops = {
.enable = clk_plle_enable,
};
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
+#ifdef CONFIG_CLK_TEGRA114
static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
unsigned long parent_rate)
@@ -1339,7 +1339,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
return clk;
}
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
+#ifdef CONFIG_CLK_TEGRA114
const struct clk_ops tegra_clk_pllxc_ops = {
.is_enabled = clk_pll_is_enabled,
.enable = clk_pll_iddq_enable,