| Message ID | 1373458313-18970-3-git-send-email-padma.v@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Padmavathi, Andrew, On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote: > From: Andrew Bresticker <abrestic@chromium.org> > > This allows the input clocks to the Exynos AudioSS block to be specified > via device-tree bindings. Default names will be used when an input clock > is not given. This will be useful when adding support for the > Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of > "sclk_audio0". > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > Reviewed-on: https://gerrit.chromium.org/gerrit/57833 > Reviewed-by: Simon Glass <sjg@chromium.org> > --- > .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 > ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-) Well, this is basically how it should be done, but in current state of clock core I can see a problem: can we really rely on the order of clock initialization? I mean, we can't defer initialization of particular clock controller until all external clocks it needs are available, because there is no probing involved here. Best regards, Tomasz
Quoting Tomasz Figa (2013-07-22 09:28:47) > Hi Padmavathi, Andrew, > > On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote: > > From: Andrew Bresticker <abrestic@chromium.org> > > > > This allows the input clocks to the Exynos AudioSS block to be specified > > via device-tree bindings. Default names will be used when an input clock > > is not given. This will be useful when adding support for the > > Exynos5420 where the audio bus clock is called "sclk_maudio0" instead of > > "sclk_audio0". > > > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > > Reviewed-on: https://gerrit.chromium.org/gerrit/57833 > > Reviewed-by: Simon Glass <sjg@chromium.org> > > --- > > .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 > > ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c | > > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 deletions(-) > > Well, this is basically how it should be done, but in current state of > clock core I can see a problem: can we really rely on the order of clock > initialization? I mean, we can't defer initialization of particular clock > controller until all external clocks it needs are available, because there > is no probing involved here. The clock core allows registering clocks even if their parents are not yet registered. I test this path with some dummy clocks every so often to make sure the re-parenting operation are completed successfully after the parents eventually are registered. This feature was not used in practice until recently with the advent of multiple clock controllers getting registered and DT description of clocks / clock controllers that may be "out of order". If you find any bugs please let me know ;-) Regards, Mike > > Best regards, > Tomasz
On Monday 22 of July 2013 11:15:30 Mike Turquette wrote: > Quoting Tomasz Figa (2013-07-22 09:28:47) > > > Hi Padmavathi, Andrew, > > > > On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote: > > > From: Andrew Bresticker <abrestic@chromium.org> > > > > > > This allows the input clocks to the Exynos AudioSS block to be > > > specified via device-tree bindings. Default names will be used > > > when an input clock is not given. This will be useful when adding > > > support for the Exynos5420 where the audio bus clock is called > > > "sclk_maudio0" instead of "sclk_audio0". > > > > > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > > > Reviewed-on: https://gerrit.chromium.org/gerrit/57833 > > > Reviewed-by: Simon Glass <sjg@chromium.org> > > > --- > > > > > > .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 > > > > > > ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c > > > |> > > > > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 > > > deletions(-) > > > > Well, this is basically how it should be done, but in current state of > > clock core I can see a problem: can we really rely on the order of > > clock initialization? I mean, we can't defer initialization of > > particular clock controller until all external clocks it needs are > > available, because there is no probing involved here. > > The clock core allows registering clocks even if their parents are not > yet registered. I test this path with some dummy clocks every so often > to make sure the re-parenting operation are completed successfully after > the parents eventually are registered. Sure it does, but this patch is about something different. It adds device tree based lookup (of_clk_get_by_name()) of external clocks (as opposed to existing lookup by name), which will fail if provider pointed by phandle is not registered yet. > This feature was not used in practice until recently with the advent of > multiple clock controllers getting registered and DT description of > clocks / clock controllers that may be "out of order". If you find any > bugs please let me know ;-) I will send you a bunch of patches sorting out issues I found in clk_set_rate() path, but give me some time to prepare them :). As for multiple clock controllers, this is going to be funny. I have discussed this a bit with Sylwester and we managed to find some design issues that I think must be solved: a) What about multiple controllers with identical clock names? Imagine two PMICs that can also generate 32 KHz clocks, both having them named "clk32k". Am I right saying that this won't work with current code? b) What are the rules of using clock-output-names property (and what should be used in non-DT case)? I can imagine using it to assign platform- specific names of clock outputs of extra clock controllers (this would help in the above case of "clk32k"), but currently it seems like it is optional to use it in clock drivers and the meaning is provider-specific. Best regards, Tomasz
Hi Tomasz, On Tue, Jul 23, 2013 at 1:12 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > On Monday 22 of July 2013 11:15:30 Mike Turquette wrote: >> Quoting Tomasz Figa (2013-07-22 09:28:47) >> >> > Hi Padmavathi, Andrew, >> > >> > On Wednesday 10 of July 2013 17:41:51 Padmavathi Venna wrote: >> > > From: Andrew Bresticker <abrestic@chromium.org> >> > > >> > > This allows the input clocks to the Exynos AudioSS block to be >> > > specified via device-tree bindings. Default names will be used >> > > when an input clock is not given. This will be useful when adding >> > > support for the Exynos5420 where the audio bus clock is called >> > > "sclk_maudio0" instead of "sclk_audio0". >> > > >> > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> >> > > Reviewed-on: https://gerrit.chromium.org/gerrit/57833 >> > > Reviewed-by: Simon Glass <sjg@chromium.org> >> > > --- >> > > >> > > .../devicetree/bindings/clock/clk-exynos-audss.txt | 31 >> > > >> > > ++++++++++++++++++- drivers/clk/samsung/clk-exynos-audss.c >> > > |> > >> > > 28 +++++++++++++++-- 2 files changed, 53 insertions(+), 6 >> > > deletions(-) >> > >> > Well, this is basically how it should be done, but in current state of >> > clock core I can see a problem: can we really rely on the order of >> > clock initialization? I mean, we can't defer initialization of >> > particular clock controller until all external clocks it needs are >> > available, because there is no probing involved here. your point is valid. In this case audio clk controller registration happening only after CMU clk controller from which audss needs clks. So this patch can't be taken in? Thanks Padma >> >> The clock core allows registering clocks even if their parents are not >> yet registered. I test this path with some dummy clocks every so often >> to make sure the re-parenting operation are completed successfully after >> the parents eventually are registered. > > Sure it does, but this patch is about something different. It adds device > tree based lookup (of_clk_get_by_name()) of external clocks (as opposed to > existing lookup by name), which will fail if provider pointed by phandle > is not registered yet. > >> This feature was not used in practice until recently with the advent of >> multiple clock controllers getting registered and DT description of >> clocks / clock controllers that may be "out of order". If you find any >> bugs please let me know ;-) > > I will send you a bunch of patches sorting out issues I found in > clk_set_rate() path, but give me some time to prepare them :). > > As for multiple clock controllers, this is going to be funny. I have > discussed this a bit with Sylwester and we managed to find some design > issues that I think must be solved: > > a) What about multiple controllers with identical clock names? Imagine two > PMICs that can also generate 32 KHz clocks, both having them named > "clk32k". Am I right saying that this won't work with current code? > > b) What are the rules of using clock-output-names property (and what > should be used in non-DT case)? I can imagine using it to assign platform- > specific names of clock outputs of extra clock controllers (this would > help in the above case of "clk32k"), but currently it seems like it is > optional to use it in clock drivers and the meaning is provider-specific. > > Best regards, > Tomasz >
Hi Tomasz, > Well, this is basically how it should be done, but in current state of > clock core I can see a problem: can we really rely on the order of clock > initialization? I mean, we can't defer initialization of particular clock > controller until all external clocks it needs are available, because there > is no probing involved here. Right, we can't. The reason I added the device-tree lookup of input clocks was because Exynos5420 has different names for several of the input clocks to the audio block. We already need a separate compatibility string because of the ADMA clock, so we could just use that to determine the parent clock names. It's not ideal, but it's a workaround for the initialization order issue. Thoughts? Thanks, Andrew
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 3115930..66d4662 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -16,6 +16,21 @@ Required Properties: - #clock-cells: should be 1. +Optional Properties: + +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", and "sclk_audio", respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -38,15 +53,27 @@ pcm_bus 8 sclk_pcm 9 adma 10 Exynos5420 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with audio bus input clock + specified is listed below. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 148>; + clock-names = "sclk_audio"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 86d2606..39d3383 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { /* register exynos_audss clocks */ void __init exynos_audss_clk_init(struct device_node *np) { + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio; + reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: failed to map audss registers\n", __func__); @@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np) clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + pll_ref = of_clk_get_by_name(np, "pll_ref"); + pll_in = of_clk_get_by_name(np, "pll_in"); + if (!IS_ERR(pll_ref)) { + mout_audss_p[0] = __clk_get_name(pll_ref); + clk_put(pll_ref); + } + if (!IS_ERR(pll_in)) { + mout_audss_p[1] = __clk_get_name(pll_in); + clk_put(pll_in); + } clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = of_clk_get_by_name(np, "cdclk"); + sclk_audio = of_clk_get_by_name(np, "sclk_audio"); + if (!IS_ERR(cdclk)) { + mout_i2s_p[1] = __clk_get_name(cdclk); + clk_put(cdclk); + } + if (!IS_ERR(sclk_audio)) { + mout_i2s_p[2] = __clk_get_name(sclk_audio); + clk_put(sclk_audio); + } clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);