| Message ID | 1374830110-30685-5-git-send-email-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 07/26/2013 03:15 AM, Joseph Lo wrote: > The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are > clock gated and SDRAM in self-refresh mode. That means the low level LP1 > suspending and resuming code couldn't be run on DRAM and the CPU must > switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And > the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. > The LP1 low level handling code need to be moved to IRAM area first. And > marking the LP1 mask for indicating the Tegra device is in LP1. The CPU > power timer needs to be re-calculated based on 32KHz that was originally > based on PCLK. > diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c > #ifdef CONFIG_PM_SLEEP > static DEFINE_SPINLOCK(tegra_lp2_lock); > +static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA); > +static u32 iram_save_size; > +static void *iram_save_addr; > +struct tegra_lp1_iram *tegra_lp1_iram; > void (*tegra_tear_down_cpu)(void); > +void (*tegra_sleep_core_finish)(unsigned long v2p); I'm not sure all of those are required to be global variables. For example, iram_code is just a constant, so you could easily just use it directly in code. > @@ -174,14 +180,75 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode( > enum tegra_suspend_mode mode) > { > /* > - * The Tegra devices only support suspending to LP2 currently. > + * The Tegra devices only support suspending to LP1 currently. That now says that only LP1 is supported. That's not true; both LP1 and LP2 are supported. How about s/LP1/LP1 or lower/ or s:LP1:LP1/LP2: ? > +static bool tegra_sleep_core_init(void) > +{ > + if (!tegra_sleep_core_finish) > + return false; > + > + return true; > +} That function seems a little pointless. Why not just check the value of tegra_sleep_core_finish directly in tegra_init_suspend()? > +static void tegra_suspend_enter_lp1(void) > +{ > + tegra_pmc_suspend(); > + > + /* copy the reset vector & SDRAM shutdown code into IRAM */ > + memcpy(iram_save_addr, iram_code, iram_save_size); > + memcpy(iram_code, tegra_lp1_iram->start_addr, iram_save_size); > + > + *((u32 *)tegra_cpu_lp1_mask) = 1; > +} > + > +static void tegra_suspend_exit_lp1(void) > +{ > + tegra_pmc_resume(); > + > + /* restore IRAM */ > + memcpy(iram_code, iram_save_addr, iram_save_size); > + > + *(u32 *)tegra_cpu_lp1_mask = 0; > +} I'm not really sure I like that, but I suppose it's OK. It sure seems like a performance limiter, but I suppose LP1 is so slow it doesn't matter, due to the need to ramp power rails, PLLs, SDRAM controller, etc. It'd be nice to simply reserve more IRAM for the kernel's use. Right now, only 1K is reserved, and presumably the code running on the AVP can't use the rest of that page anyway, or can it? > @@ -212,9 +282,15 @@ static int tegra_suspend_enter(suspend_state_t state) > break; > } > > - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); > + if (mode == TEGRA_SUSPEND_LP2) > + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); > + else > + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_core); Nit: It might be slightly simpler to simply calculate the parameter to cpu_suspend(), but then take the same code-path: if (mode == TEGRA_SUSPEND_LP2) sleep_func = tegra_sleep_cpu; else sleep_func = tegra_sleep_core; cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, sleep_func); That way, it's a little more obvious that the code always calls cpu_suspend() in the same way, but simply passes a different function to it to power things down at the end. > diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c > void tegra_pmc_pm_set(enum tegra_suspend_mode mode) > { > u32 reg, csr_reg; > - unsigned long rate = 0; > + unsigned long rate = 32768; That's LP1-specific. You should add a "case TEGRA_SUSPEND_LP1:" to the switch statement that calculates rate instead; after all, that's the whole point of having that switch statement.
On Tue, 2013-07-30 at 07:13 +0800, Stephen Warren wrote: > On 07/26/2013 03:15 AM, Joseph Lo wrote: > > The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are > > clock gated and SDRAM in self-refresh mode. That means the low level LP1 > > suspending and resuming code couldn't be run on DRAM and the CPU must > > switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And > > the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. > > The LP1 low level handling code need to be moved to IRAM area first. And > > marking the LP1 mask for indicating the Tegra device is in LP1. The CPU > > power timer needs to be re-calculated based on 32KHz that was originally > > based on PCLK. > > > diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c > > > #ifdef CONFIG_PM_SLEEP > > static DEFINE_SPINLOCK(tegra_lp2_lock); > > +static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA); > > +static u32 iram_save_size; > > +static void *iram_save_addr; > > +struct tegra_lp1_iram *tegra_lp1_iram; > > void (*tegra_tear_down_cpu)(void); > > +void (*tegra_sleep_core_finish)(unsigned long v2p); > > I'm not sure all of those are required to be global variables. For > example, iram_code is just a constant, so you could easily just use it > directly in code. > All of them does not mean the same thing. The LP1 resume code was built in kernel image and store in RAM. The tegra_lp1_iram hooks the LP1 resume code for different chips. Before LP1 suspend, the original stuffs that in the area of IRAM would be store in the iram_save_addr (RAM). Then copy the LP1 resume code to iram_code area (IRAM). > > +static bool tegra_sleep_core_init(void) > > +{ > > + if (!tegra_sleep_core_finish) > > + return false; > > + > > + return true; > > +} > > That function seems a little pointless. Why not just check the value of > tegra_sleep_core_finish directly in tegra_init_suspend()? > I will add some code that wraps to different SoC later. We add some common code for LP1 support here, but it didn't support by the chip yet. Does that OK or should I move it to the next patch? > > +static void tegra_suspend_enter_lp1(void) > > +{ > > + tegra_pmc_suspend(); > > + > > + /* copy the reset vector & SDRAM shutdown code into IRAM */ > > + memcpy(iram_save_addr, iram_code, iram_save_size); > > + memcpy(iram_code, tegra_lp1_iram->start_addr, iram_save_size); > > + > > + *((u32 *)tegra_cpu_lp1_mask) = 1; > > +} > > + > > +static void tegra_suspend_exit_lp1(void) > > +{ > > + tegra_pmc_resume(); > > + > > + /* restore IRAM */ > > + memcpy(iram_code, iram_save_addr, iram_save_size); > > + > > + *(u32 *)tegra_cpu_lp1_mask = 0; > > +} > > I'm not really sure I like that, but I suppose it's OK. It sure seems > like a performance limiter, but I suppose LP1 is so slow it doesn't > matter, due to the need to ramp power rails, PLLs, SDRAM controller, etc. > That's why we only back up the code size that exactly same with the LP1 resume code of the SoC. > It'd be nice to simply reserve more IRAM for the kernel's use. Right > now, only 1K is reserved, and presumably the code running on the AVP > can't use the rest of that page anyway, or can it? The LP1 resume code still running on the CPU (The LP0 would resume from AVP). > > > @@ -212,9 +282,15 @@ static int tegra_suspend_enter(suspend_state_t state) > > break; > > } > > > > - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); > > + if (mode == TEGRA_SUSPEND_LP2) > > + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); > > + else > > + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_core); > > Nit: It might be slightly simpler to simply calculate the parameter to > cpu_suspend(), but then take the same code-path: > > if (mode == TEGRA_SUSPEND_LP2) > sleep_func = tegra_sleep_cpu; > else > sleep_func = tegra_sleep_core; > cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, sleep_func); > > That way, it's a little more obvious that the code always calls > cpu_suspend() in the same way, but simply passes a different function to > it to power things down at the end. OK. Will do. > > > diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c > > > void tegra_pmc_pm_set(enum tegra_suspend_mode mode) > > { > > u32 reg, csr_reg; > > - unsigned long rate = 0; > > + unsigned long rate = 32768; > > That's LP1-specific. You should add a "case TEGRA_SUSPEND_LP1:" to the > switch statement that calculates rate instead; after all, that's the > whole point of having that switch statement. Will fix.
On 08/02/2013 03:27 AM, Joseph Lo wrote: > On Tue, 2013-07-30 at 07:13 +0800, Stephen Warren wrote: >> On 07/26/2013 03:15 AM, Joseph Lo wrote: >>> The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are >>> clock gated and SDRAM in self-refresh mode. That means the low level LP1 >>> suspending and resuming code couldn't be run on DRAM and the CPU must >>> switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And >>> the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. >>> The LP1 low level handling code need to be moved to IRAM area first. And >>> marking the LP1 mask for indicating the Tegra device is in LP1. The CPU >>> power timer needs to be re-calculated based on 32KHz that was originally >>> based on PCLK. >> >>> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c >> >>> #ifdef CONFIG_PM_SLEEP >>> static DEFINE_SPINLOCK(tegra_lp2_lock); >>> +static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA); >>> +static u32 iram_save_size; >>> +static void *iram_save_addr; >>> +struct tegra_lp1_iram *tegra_lp1_iram; >>> void (*tegra_tear_down_cpu)(void); >>> +void (*tegra_sleep_core_finish)(unsigned long v2p); >> >> I'm not sure all of those are required to be global variables. For >> example, iram_code is just a constant, so you could easily just use it >> directly in code. > > All of them does not mean the same thing. The LP1 resume code was built > in kernel image and store in RAM. > The tegra_lp1_iram hooks the LP1 resume code for different chips. Before > LP1 suspend, the original stuffs that in the area of IRAM would be store > in the iram_save_addr (RAM). Then copy the LP1 resume code to iram_code > area (IRAM). Sure, some of those variable may differ based on the SoC at runtime etc. But at least the value of iram_code never changes, right? >>> +static bool tegra_sleep_core_init(void) >>> +{ >>> + if (!tegra_sleep_core_finish) >>> + return false; >>> + >>> + return true; >>> +} >> >> That function seems a little pointless. Why not just check the value of >> tegra_sleep_core_finish directly in tegra_init_suspend()? > > I will add some code that wraps to different SoC later. We add some > common code for LP1 support here, but it didn't support by the chip yet. > Does that OK or should I move it to the next patch? OK, I see this is enhanced immediately in the next patch, so it's fine. >>> +static void tegra_suspend_enter_lp1(void) >>> +{ >>> + tegra_pmc_suspend(); >>> + >>> + /* copy the reset vector & SDRAM shutdown code into IRAM */ >>> + memcpy(iram_save_addr, iram_code, iram_save_size); >>> + memcpy(iram_code, tegra_lp1_iram->start_addr, iram_save_size); >>> + >>> + *((u32 *)tegra_cpu_lp1_mask) = 1; >>> +} >>> + >>> +static void tegra_suspend_exit_lp1(void) >>> +{ >>> + tegra_pmc_resume(); >>> + >>> + /* restore IRAM */ >>> + memcpy(iram_code, iram_save_addr, iram_save_size); >>> + >>> + *(u32 *)tegra_cpu_lp1_mask = 0; >>> +} >> >> I'm not really sure I like that, but I suppose it's OK. It sure seems >> like a performance limiter, but I suppose LP1 is so slow it doesn't >> matter, due to the need to ramp power rails, PLLs, SDRAM controller, etc. > > That's why we only back up the code size that exactly same with the LP1 > resume code of the SoC. > >> It'd be nice to simply reserve more IRAM for the kernel's use. Right >> now, only 1K is reserved, and presumably the code running on the AVP >> can't use the rest of that page anyway, or can it? > > The LP1 resume code still running on the CPU (The LP0 would resume from > AVP). Sure. However, if the AVP never touched the IRAM region where the LP1 resume code is placed, we would only need to copy the LP1 resume code to IRAM once at kernel boot time, rather than every time we enter/leave LP1. I guess the idea is that once we have an AVP driver, we will force the AVP to suspend first, save the IRAM that it might have been using, do the system suspend/resume, then restore the IRAM. And that changing that sequence so that the AVP never ever touched the LP1 IRAM area would require AVP firmware changes that we can't make?
On Sat, 2013-08-03 at 04:40 +0800, Stephen Warren wrote: > On 08/02/2013 03:27 AM, Joseph Lo wrote: > > On Tue, 2013-07-30 at 07:13 +0800, Stephen Warren wrote: > >> On 07/26/2013 03:15 AM, Joseph Lo wrote: > >>> The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are > >>> clock gated and SDRAM in self-refresh mode. That means the low level LP1 > >>> suspending and resuming code couldn't be run on DRAM and the CPU must > >>> switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And > >>> the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. > >>> The LP1 low level handling code need to be moved to IRAM area first. And > >>> marking the LP1 mask for indicating the Tegra device is in LP1. The CPU > >>> power timer needs to be re-calculated based on 32KHz that was originally > >>> based on PCLK. > >> > >>> diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c > >> > >>> #ifdef CONFIG_PM_SLEEP > >>> static DEFINE_SPINLOCK(tegra_lp2_lock); > >>> +static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA); > >>> +static u32 iram_save_size; > >>> +static void *iram_save_addr; > >>> +struct tegra_lp1_iram *tegra_lp1_iram; > >>> void (*tegra_tear_down_cpu)(void); > >>> +void (*tegra_sleep_core_finish)(unsigned long v2p); > >> > >> I'm not sure all of those are required to be global variables. For > >> example, iram_code is just a constant, so you could easily just use it > >> directly in code. > > > > All of them does not mean the same thing. The LP1 resume code was built > > in kernel image and store in RAM. > > The tegra_lp1_iram hooks the LP1 resume code for different chips. Before > > LP1 suspend, the original stuffs that in the area of IRAM would be store > > in the iram_save_addr (RAM). Then copy the LP1 resume code to iram_code > > area (IRAM). > > Sure, some of those variable may differ based on the SoC at runtime etc. > > But at least the value of iram_code never changes, right? Yes. > >>> +static void tegra_suspend_enter_lp1(void) > >>> +{ > >>> + tegra_pmc_suspend(); > >>> + > >>> + /* copy the reset vector & SDRAM shutdown code into IRAM */ > >>> + memcpy(iram_save_addr, iram_code, iram_save_size); > >>> + memcpy(iram_code, tegra_lp1_iram->start_addr, iram_save_size); > >>> + > >>> + *((u32 *)tegra_cpu_lp1_mask) = 1; > >>> +} > >>> + > >>> +static void tegra_suspend_exit_lp1(void) > >>> +{ > >>> + tegra_pmc_resume(); > >>> + > >>> + /* restore IRAM */ > >>> + memcpy(iram_code, iram_save_addr, iram_save_size); > >>> + > >>> + *(u32 *)tegra_cpu_lp1_mask = 0; > >>> +} > >> > >> I'm not really sure I like that, but I suppose it's OK. It sure seems > >> like a performance limiter, but I suppose LP1 is so slow it doesn't > >> matter, due to the need to ramp power rails, PLLs, SDRAM controller, etc. > > > > That's why we only back up the code size that exactly same with the LP1 > > resume code of the SoC. > > > >> It'd be nice to simply reserve more IRAM for the kernel's use. Right > >> now, only 1K is reserved, and presumably the code running on the AVP > >> can't use the rest of that page anyway, or can it? > > > > The LP1 resume code still running on the CPU (The LP0 would resume from > > AVP). > > Sure. However, if the AVP never touched the IRAM region where the LP1 > resume code is placed, we would only need to copy the LP1 resume code to > IRAM once at kernel boot time, rather than every time we enter/leave LP1. > > I guess the idea is that once we have an AVP driver, we will force the > AVP to suspend first, save the IRAM that it might have been using, do > the system suspend/resume, then restore the IRAM. And that changing that > sequence so that the AVP never ever touched the LP1 IRAM area would > require AVP firmware changes that we can't make? Yes, exactly.
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 5792872..45c9516 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -37,12 +37,18 @@ #include "reset.h" #include "flowctrl.h" #include "fuse.h" +#include "pm.h" #include "pmc.h" #include "sleep.h" #ifdef CONFIG_PM_SLEEP static DEFINE_SPINLOCK(tegra_lp2_lock); +static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA); +static u32 iram_save_size; +static void *iram_save_addr; +struct tegra_lp1_iram *tegra_lp1_iram; void (*tegra_tear_down_cpu)(void); +void (*tegra_sleep_core_finish)(unsigned long v2p); static void tegra_tear_down_cpu_init(void) { @@ -174,14 +180,75 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode( enum tegra_suspend_mode mode) { /* - * The Tegra devices only support suspending to LP2 currently. + * The Tegra devices only support suspending to LP1 currently. */ - if (mode > TEGRA_SUSPEND_LP2) - return TEGRA_SUSPEND_LP2; + if (mode > TEGRA_SUSPEND_LP1) + return TEGRA_SUSPEND_LP1; return mode; } +static int tegra_sleep_core(unsigned long v2p) +{ + setup_mm_for_reboot(); + tegra_sleep_core_finish(v2p); + + /* should never here */ + BUG(); + + return 0; +} + +/* + * tegra_lp1_iram_hook + * + * Hooking the address of LP1 reset vector and SDRAM self-refresh code in + * SDRAM. These codes not be copied to IRAM in this fuction. We need to + * copy these code to IRAM before LP0/LP1 suspend and restore the content + * of IRAM after resume. + */ +static bool tegra_lp1_iram_hook(void) +{ + if (!tegra_lp1_iram) + return false; + + iram_save_size = tegra_lp1_iram->end_addr - tegra_lp1_iram->start_addr; + iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); + if (!iram_save_addr) + return false; + + return true; +} + +static bool tegra_sleep_core_init(void) +{ + if (!tegra_sleep_core_finish) + return false; + + return true; +} + +static void tegra_suspend_enter_lp1(void) +{ + tegra_pmc_suspend(); + + /* copy the reset vector & SDRAM shutdown code into IRAM */ + memcpy(iram_save_addr, iram_code, iram_save_size); + memcpy(iram_code, tegra_lp1_iram->start_addr, iram_save_size); + + *((u32 *)tegra_cpu_lp1_mask) = 1; +} + +static void tegra_suspend_exit_lp1(void) +{ + tegra_pmc_resume(); + + /* restore IRAM */ + memcpy(iram_code, iram_save_addr, iram_save_size); + + *(u32 *)tegra_cpu_lp1_mask = 0; +} + static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { [TEGRA_SUSPEND_NONE] = "none", [TEGRA_SUSPEND_LP2] = "LP2", @@ -205,6 +272,9 @@ static int tegra_suspend_enter(suspend_state_t state) suspend_cpu_complex(); switch (mode) { + case TEGRA_SUSPEND_LP1: + tegra_suspend_enter_lp1(); + break; case TEGRA_SUSPEND_LP2: tegra_set_cpu_in_lp2(); break; @@ -212,9 +282,15 @@ static int tegra_suspend_enter(suspend_state_t state) break; } - cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + if (mode == TEGRA_SUSPEND_LP2) + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); + else + cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_core); switch (mode) { + case TEGRA_SUSPEND_LP1: + tegra_suspend_exit_lp1(); + break; case TEGRA_SUSPEND_LP2: tegra_clear_cpu_in_lp2(); break; @@ -235,12 +311,23 @@ static const struct platform_suspend_ops tegra_suspend_ops = { void __init tegra_init_suspend(void) { - if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) + enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); + + if (mode == TEGRA_SUSPEND_NONE) return; tegra_tear_down_cpu_init(); tegra_pmc_suspend_init(); + if (mode >= TEGRA_SUSPEND_LP1) { + if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { + pr_err("%s: unable to allocate memory for SDRAM" + "self-refresh -- LP0/LP1 unavailable\n", + __func__); + tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); + } + } + suspend_set_ops(&tegra_suspend_ops); } #endif diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 94c4b9d..3cb9309 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -23,6 +23,13 @@ #include "pmc.h" +struct tegra_lp1_iram { + void *start_addr; + void *end_addr; +}; +extern struct tegra_lp1_iram *tegra_lp1_iram; +extern void (*tegra_sleep_core_finish)(unsigned long v2p); + extern unsigned long l2x0_saved_regs_addr; void save_cpu_arch_register(void); diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 018bc87..dff239f 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -196,10 +196,28 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) return pmc_pm_data.suspend_mode; } +void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) +{ + if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) + return; + + pmc_pm_data.suspend_mode = mode; +} + +void tegra_pmc_suspend(void) +{ + tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); +} + +void tegra_pmc_resume(void) +{ + tegra_pmc_writel(0x0, PMC_SCRATCH41); +} + void tegra_pmc_pm_set(enum tegra_suspend_mode mode) { u32 reg, csr_reg; - unsigned long rate = 0; + unsigned long rate = 32768; reg = tegra_pmc_readl(PMC_CTRL); reg |= TEGRA_POWER_CPU_PWRREQ_OE; diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h index e1c2df2..549f8c7 100644 --- a/arch/arm/mach-tegra/pmc.h +++ b/arch/arm/mach-tegra/pmc.h @@ -28,6 +28,9 @@ enum tegra_suspend_mode { #ifdef CONFIG_PM_SLEEP enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); +void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); +void tegra_pmc_suspend(void); +void tegra_pmc_resume(void); void tegra_pmc_pm_set(enum tegra_suspend_mode mode); void tegra_pmc_suspend_init(void); #endif diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index c90d8e9..76a9343 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -39,6 +39,10 @@ void __tegra_cpu_reset_handler_end(void); void tegra_secondary_startup(void); #ifdef CONFIG_PM_SLEEP +#define tegra_cpu_lp1_mask \ + (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ + ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ + (u32)__tegra_cpu_reset_handler_start))) #define tegra_cpu_lp2_mask \ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm/mach-tegra/pm.c | 97 ++++++++++++++++++++++++++++++++++++++++++--- arch/arm/mach-tegra/pm.h | 7 ++++ arch/arm/mach-tegra/pmc.c | 20 +++++++++- arch/arm/mach-tegra/pmc.h | 3 ++ arch/arm/mach-tegra/reset.h | 4 ++ 5 files changed, 125 insertions(+), 6 deletions(-)