diff mbox

drm/radeon/si: Add support for CP DMA to CS checker for compute v2

Message ID 1376689659-2703-1-git-send-email-tom@stellard.net (mailing list archive)
State New, archived
Headers show

Commit Message

Tom Stellard Aug. 16, 2013, 9:47 p.m. UTC 
From: Tom Stellard <thomas.stellard@amd.com>

Also add a new RADEON_INFO query to check that CP DMA packets are
supported on the compute ring.

v2:
  - Don't bump kms version, so this patch can be backported to stable
    kernels.

Cc: stable@vger.kernel.org
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
---
 drivers/gpu/drm/radeon/radeon_kms.c |   3 +
 drivers/gpu/drm/radeon/si.c         | 106 +++++++++++++++++++++---------------
 include/uapi/drm/radeon_drm.h       |   2 +
 3 files changed, 66 insertions(+), 45 deletions(-)

Comments

Greg KH Aug. 16, 2013, 10:34 p.m. UTC | #1 
On Fri, Aug 16, 2013 at 05:47:39PM -0400, Tom Stellard wrote:
> From: Tom Stellard <thomas.stellard@amd.com>
> 
> Also add a new RADEON_INFO query to check that CP DMA packets are
> supported on the compute ring.
> 
> v2:
>   - Don't bump kms version, so this patch can be backported to stable
>     kernels.

Why is this for a stable kernel?  What reported problem does it fix?

thanks,

greg k-h
Tom Stellard Aug. 17, 2013, 12:31 a.m. UTC | #2 
On Fri, Aug 16, 2013 at 03:34:09PM -0700, Greg KH wrote:
> On Fri, Aug 16, 2013 at 05:47:39PM -0400, Tom Stellard wrote:
> > From: Tom Stellard <thomas.stellard@amd.com>
> > 
> > Also add a new RADEON_INFO query to check that CP DMA packets are
> > supported on the compute ring.
> > 
> > v2:
> >   - Don't bump kms version, so this patch can be backported to stable
> >     kernels.
> 
> Why is this for a stable kernel?  What reported problem does it fix?
> 

CP DMA has been supported since the 3.8 kernel, but due to an oversight
we forgot to teach the CS checker that the CP DMA packet was legal for
the compute ring on Southern Islands GPUs.

This patch fixes a bug where the radeon driver will incorrectly reject a legal
CP DMA packet from user space.  I would like to have the patch
backported to stable so that we don't have to require Mesa users to use a
bleeding edge kernel in order to take advantage of this feature which
is already present in the stable kernels (3.8 and newer).

-Tom
Greg KH Aug. 17, 2013, 12:42 a.m. UTC | #3 
On Fri, Aug 16, 2013 at 05:31:39PM -0700, Tom Stellard wrote:
> On Fri, Aug 16, 2013 at 03:34:09PM -0700, Greg KH wrote:
> > On Fri, Aug 16, 2013 at 05:47:39PM -0400, Tom Stellard wrote:
> > > From: Tom Stellard <thomas.stellard@amd.com>
> > > 
> > > Also add a new RADEON_INFO query to check that CP DMA packets are
> > > supported on the compute ring.
> > > 
> > > v2:
> > >   - Don't bump kms version, so this patch can be backported to stable
> > >     kernels.
> > 
> > Why is this for a stable kernel?  What reported problem does it fix?
> > 
> 
> CP DMA has been supported since the 3.8 kernel, but due to an oversight
> we forgot to teach the CS checker that the CP DMA packet was legal for
> the compute ring on Southern Islands GPUs.
> 
> This patch fixes a bug where the radeon driver will incorrectly reject a legal
> CP DMA packet from user space.  I would like to have the patch
> backported to stable so that we don't have to require Mesa users to use a
> bleeding edge kernel in order to take advantage of this feature which
> is already present in the stable kernels (3.8 and newer).

Then please put that in the changelog section of the patch, otherwise
people (like me), will ask these types of things :)

thanks,

greg k-h
Alex Deucher Aug. 19, 2013, 4:42 p.m. UTC | #4 
On Fri, Aug 16, 2013 at 5:47 PM, Tom Stellard <tom@stellard.net> wrote:
>
> From: Tom Stellard <thomas.stellard@amd.com>
>
> Also add a new RADEON_INFO query to check that CP DMA packets are
> supported on the compute ring.
>
> v2:
>   - Don't bump kms version, so this patch can be backported to stable
>     kernels.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Tom Stellard <thomas.stellard@amd.com>

I've applied this to my tree and updated the the commit regarding why
it needs to go to stable.

Thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/radeon_kms.c |   3 +
>  drivers/gpu/drm/radeon/si.c         | 106 +++++++++++++++++++++---------------
>  include/uapi/drm/radeon_drm.h       |   2 +
>  3 files changed, 66 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
> index 49ff3d1..cc2ca38 100644
> --- a/drivers/gpu/drm/radeon/radeon_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -433,6 +433,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
>                         return -EINVAL;
>                 }
>                 break;
> +       case RADEON_INFO_SI_CP_DMA_COMPUTE:
> +               *value = 1;
> +               break;
>         default:
>                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
>                 return -EINVAL;
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index daa8d2d..8a21132 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4083,13 +4083,64 @@ static int si_vm_packet3_ce_check(struct radeon_device *rdev,
>         return 0;
>  }
>
> +static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
> +{
> +       u32 start_reg, reg, i;
> +       u32 command = ib[idx + 4];
> +       u32 info = ib[idx + 1];
> +       u32 idx_value = ib[idx];
> +       if (command & PACKET3_CP_DMA_CMD_SAS) {
> +               /* src address space is register */
> +               if (((info & 0x60000000) >> 29) == 0) {
> +                       start_reg = idx_value << 2;
> +                       if (command & PACKET3_CP_DMA_CMD_SAIC) {
> +                               reg = start_reg;
> +                               if (!si_vm_reg_valid(reg)) {
> +                                       DRM_ERROR("CP DMA Bad SRC register\n");
> +                                       return -EINVAL;
> +                               }
> +                       } else {
> +                               for (i = 0; i < (command & 0x1fffff); i++) {
> +                                       reg = start_reg + (4 * i);
> +                                       if (!si_vm_reg_valid(reg)) {
> +                                               DRM_ERROR("CP DMA Bad SRC register\n");
> +                                               return -EINVAL;
> +                                       }
> +                               }
> +                       }
> +               }
> +       }
> +       if (command & PACKET3_CP_DMA_CMD_DAS) {
> +               /* dst address space is register */
> +               if (((info & 0x00300000) >> 20) == 0) {
> +                       start_reg = ib[idx + 2];
> +                       if (command & PACKET3_CP_DMA_CMD_DAIC) {
> +                               reg = start_reg;
> +                               if (!si_vm_reg_valid(reg)) {
> +                                       DRM_ERROR("CP DMA Bad DST register\n");
> +                                       return -EINVAL;
> +                               }
> +                       } else {
> +                               for (i = 0; i < (command & 0x1fffff); i++) {
> +                                       reg = start_reg + (4 * i);
> +                               if (!si_vm_reg_valid(reg)) {
> +                                               DRM_ERROR("CP DMA Bad DST register\n");
> +                                               return -EINVAL;
> +                                       }
> +                               }
> +                       }
> +               }
> +       }
> +       return 0;
> +}
> +
>  static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
>                                    u32 *ib, struct radeon_cs_packet *pkt)
>  {
> +       int r;
>         u32 idx = pkt->idx + 1;
>         u32 idx_value = ib[idx];
>         u32 start_reg, end_reg, reg, i;
> -       u32 command, info;
>
>         switch (pkt->opcode) {
>         case PACKET3_NOP:
> @@ -4190,50 +4241,9 @@ static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
>                 }
>                 break;
>         case PACKET3_CP_DMA:
> -               command = ib[idx + 4];
> -               info = ib[idx + 1];
> -               if (command & PACKET3_CP_DMA_CMD_SAS) {
> -                       /* src address space is register */
> -                       if (((info & 0x60000000) >> 29) == 0) {
> -                               start_reg = idx_value << 2;
> -                               if (command & PACKET3_CP_DMA_CMD_SAIC) {
> -                                       reg = start_reg;
> -                                       if (!si_vm_reg_valid(reg)) {
> -                                               DRM_ERROR("CP DMA Bad SRC register\n");
> -                                               return -EINVAL;
> -                                       }
> -                               } else {
> -                                       for (i = 0; i < (command & 0x1fffff); i++) {
> -                                               reg = start_reg + (4 * i);
> -                                               if (!si_vm_reg_valid(reg)) {
> -                                                       DRM_ERROR("CP DMA Bad SRC register\n");
> -                                                       return -EINVAL;
> -                                               }
> -                                       }
> -                               }
> -                       }
> -               }
> -               if (command & PACKET3_CP_DMA_CMD_DAS) {
> -                       /* dst address space is register */
> -                       if (((info & 0x00300000) >> 20) == 0) {
> -                               start_reg = ib[idx + 2];
> -                               if (command & PACKET3_CP_DMA_CMD_DAIC) {
> -                                       reg = start_reg;
> -                                       if (!si_vm_reg_valid(reg)) {
> -                                               DRM_ERROR("CP DMA Bad DST register\n");
> -                                               return -EINVAL;
> -                                       }
> -                               } else {
> -                                       for (i = 0; i < (command & 0x1fffff); i++) {
> -                                               reg = start_reg + (4 * i);
> -                                               if (!si_vm_reg_valid(reg)) {
> -                                                       DRM_ERROR("CP DMA Bad DST register\n");
> -                                                       return -EINVAL;
> -                                               }
> -                                       }
> -                               }
> -                       }
> -               }
> +               r = si_vm_packet3_cp_dma_check(ib, idx);
> +               if (r)
> +                       return r;
>                 break;
>         default:
>                 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
> @@ -4245,6 +4255,7 @@ static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
>  static int si_vm_packet3_compute_check(struct radeon_device *rdev,
>                                        u32 *ib, struct radeon_cs_packet *pkt)
>  {
> +       int r;
>         u32 idx = pkt->idx + 1;
>         u32 idx_value = ib[idx];
>         u32 start_reg, reg, i;
> @@ -4317,6 +4328,11 @@ static int si_vm_packet3_compute_check(struct radeon_device *rdev,
>                                 return -EINVAL;
>                 }
>                 break;
> +       case PACKET3_CP_DMA:
> +               r = si_vm_packet3_cp_dma_check(ib, idx);
> +               if (r)
> +                       return r;
> +               break;
>         default:
>                 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
>                 return -EINVAL;
> diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
> index 321d4ac..fa8b3ad 100644
> --- a/include/uapi/drm/radeon_drm.h
> +++ b/include/uapi/drm/radeon_drm.h
> @@ -979,6 +979,8 @@ struct drm_radeon_cs {
>  #define RADEON_INFO_RING_WORKING       0x15
>  /* SI tile mode array */
>  #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
> +/* query if CP DMA is supported on the compute ring */
> +#define RADEON_INFO_SI_CP_DMA_COMPUTE  0x17
>
>
>  struct drm_radeon_info {
> --
> 1.8.1.5
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 49ff3d1..cc2ca38 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -433,6 +433,9 @@  int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			return -EINVAL;
 		}
 		break;
+	case RADEON_INFO_SI_CP_DMA_COMPUTE:
+		*value = 1;
+		break;
 	default:
 		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index daa8d2d..8a21132 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4083,13 +4083,64 @@  static int si_vm_packet3_ce_check(struct radeon_device *rdev,
 	return 0;
 }
 
+static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
+{
+	u32 start_reg, reg, i;
+	u32 command = ib[idx + 4];
+	u32 info = ib[idx + 1];
+	u32 idx_value = ib[idx];
+	if (command & PACKET3_CP_DMA_CMD_SAS) {
+		/* src address space is register */
+		if (((info & 0x60000000) >> 29) == 0) {
+			start_reg = idx_value << 2;
+			if (command & PACKET3_CP_DMA_CMD_SAIC) {
+				reg = start_reg;
+				if (!si_vm_reg_valid(reg)) {
+					DRM_ERROR("CP DMA Bad SRC register\n");
+					return -EINVAL;
+				}
+			} else {
+				for (i = 0; i < (command & 0x1fffff); i++) {
+					reg = start_reg + (4 * i);
+					if (!si_vm_reg_valid(reg)) {
+						DRM_ERROR("CP DMA Bad SRC register\n");
+						return -EINVAL;
+					}
+				}
+			}
+		}
+	}
+	if (command & PACKET3_CP_DMA_CMD_DAS) {
+		/* dst address space is register */
+		if (((info & 0x00300000) >> 20) == 0) {
+			start_reg = ib[idx + 2];
+			if (command & PACKET3_CP_DMA_CMD_DAIC) {
+				reg = start_reg;
+				if (!si_vm_reg_valid(reg)) {
+					DRM_ERROR("CP DMA Bad DST register\n");
+					return -EINVAL;
+				}
+			} else {
+				for (i = 0; i < (command & 0x1fffff); i++) {
+					reg = start_reg + (4 * i);
+				if (!si_vm_reg_valid(reg)) {
+						DRM_ERROR("CP DMA Bad DST register\n");
+						return -EINVAL;
+					}
+				}
+			}
+		}
+	}
+	return 0;
+}
+
 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
 				   u32 *ib, struct radeon_cs_packet *pkt)
 {
+	int r;
 	u32 idx = pkt->idx + 1;
 	u32 idx_value = ib[idx];
 	u32 start_reg, end_reg, reg, i;
-	u32 command, info;
 
 	switch (pkt->opcode) {
 	case PACKET3_NOP:
@@ -4190,50 +4241,9 @@  static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
 		}
 		break;
 	case PACKET3_CP_DMA:
-		command = ib[idx + 4];
-		info = ib[idx + 1];
-		if (command & PACKET3_CP_DMA_CMD_SAS) {
-			/* src address space is register */
-			if (((info & 0x60000000) >> 29) == 0) {
-				start_reg = idx_value << 2;
-				if (command & PACKET3_CP_DMA_CMD_SAIC) {
-					reg = start_reg;
-					if (!si_vm_reg_valid(reg)) {
-						DRM_ERROR("CP DMA Bad SRC register\n");
-						return -EINVAL;
-					}
-				} else {
-					for (i = 0; i < (command & 0x1fffff); i++) {
-						reg = start_reg + (4 * i);
-						if (!si_vm_reg_valid(reg)) {
-							DRM_ERROR("CP DMA Bad SRC register\n");
-							return -EINVAL;
-						}
-					}
-				}
-			}
-		}
-		if (command & PACKET3_CP_DMA_CMD_DAS) {
-			/* dst address space is register */
-			if (((info & 0x00300000) >> 20) == 0) {
-				start_reg = ib[idx + 2];
-				if (command & PACKET3_CP_DMA_CMD_DAIC) {
-					reg = start_reg;
-					if (!si_vm_reg_valid(reg)) {
-						DRM_ERROR("CP DMA Bad DST register\n");
-						return -EINVAL;
-					}
-				} else {
-					for (i = 0; i < (command & 0x1fffff); i++) {
-						reg = start_reg + (4 * i);
-						if (!si_vm_reg_valid(reg)) {
-							DRM_ERROR("CP DMA Bad DST register\n");
-							return -EINVAL;
-						}
-					}
-				}
-			}
-		}
+		r = si_vm_packet3_cp_dma_check(ib, idx);
+		if (r)
+			return r;
 		break;
 	default:
 		DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
@@ -4245,6 +4255,7 @@  static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
 				       u32 *ib, struct radeon_cs_packet *pkt)
 {
+	int r;
 	u32 idx = pkt->idx + 1;
 	u32 idx_value = ib[idx];
 	u32 start_reg, reg, i;
@@ -4317,6 +4328,11 @@  static int si_vm_packet3_compute_check(struct radeon_device *rdev,
 				return -EINVAL;
 		}
 		break;
+	case PACKET3_CP_DMA:
+		r = si_vm_packet3_cp_dma_check(ib, idx);
+		if (r)
+			return r;
+		break;
 	default:
 		DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
 		return -EINVAL;
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 321d4ac..fa8b3ad 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -979,6 +979,8 @@  struct drm_radeon_cs {
 #define RADEON_INFO_RING_WORKING	0x15
 /* SI tile mode array */
 #define RADEON_INFO_SI_TILE_MODE_ARRAY	0x16
+/* query if CP DMA is supported on the compute ring */
+#define RADEON_INFO_SI_CP_DMA_COMPUTE	0x17
 
 
 struct drm_radeon_info {