| Message ID | 20130925235214.22061.8047.stgit@Graphine (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | 89c1f60746106755e29dcc3db9f22e37000891ef |
| Headers | show |
On Thursday 26 September 2013 05:22 AM, Trent Piepho wrote: > Now that spi_device->mode is a u16, the chip_select, bits_per_mode, > and mode fields pack poorly, taking 8 bytes: four data and four > padding. By moving (u8)bits_per_word up one position, to after > (u8)chip_select, they pack better and only use 4 bytes. > > Signed-off-by: Trent Piepho<tpiepho@gmail.com> > --- > include/linux/spi/spi.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h > index 887116d..beaffe8 100644 > --- a/include/linux/spi/spi.h > +++ b/include/linux/spi/spi.h > @@ -74,6 +74,7 @@ struct spi_device { > struct spi_master *master; > u32 max_speed_hz; > u8 chip_select; > + u8 bits_per_word; > u16 mode; > #define SPI_CPHA 0x01 /* clock phase */ > #define SPI_CPOL 0x02 /* clock polarity */ > @@ -91,7 +92,6 @@ struct spi_device { > #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ > #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ > #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ > - u8 bits_per_word; > int irq; > void *controller_state; > void *controller_data; > Reviewed-by: Sourav Poddar<sourav.poddar@ti.com> Tested-by: Sourav Poddar<sourav.poddar@ti.com> ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60133471&iu=/4140/ostg.clktrk
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 887116d..beaffe8 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -74,6 +74,7 @@ struct spi_device { struct spi_master *master; u32 max_speed_hz; u8 chip_select; + u8 bits_per_word; u16 mode; #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ @@ -91,7 +92,6 @@ struct spi_device { #define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ #define SPI_RX_DUAL 0x400 /* receive with 2 wires */ #define SPI_RX_QUAD 0x800 /* receive with 4 wires */ - u8 bits_per_word; int irq; void *controller_state; void *controller_data;
Now that spi_device->mode is a u16, the chip_select, bits_per_mode, and mode fields pack poorly, taking 8 bytes: four data and four padding. By moving (u8)bits_per_word up one position, to after (u8)chip_select, they pack better and only use 4 bytes. Signed-off-by: Trent Piepho <tpiepho@gmail.com> --- include/linux/spi/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60133471&iu=/4140/ostg.clktrk