new file mode 100644
@@ -0,0 +1,99 @@
+Device Tree Clock bindings for arch-hi3xxx
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties for mux clocks:
+ - compatible : shall be "hisilicon,clk-mux".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+ be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - reg : the mux register address. It should be the offset of the container.
+ - clkmux-mask : mask bits of the mux register.
+ - clkmux-table : array of mux select bits.
+
+Optional properties for mux clocks:
+ - clkmux-hiword-mask : indicates that the bit[31:16] are the hiword mask
+ of mux selected bits (bit[15:0]). The bit[15:0] is valid only when
+ bit[31:16] is set.
+
+
+
+Required properties for gate clocks:
+ - compatible : shall be "hisilicon,clk-gate".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+ be the reference clock.
+ - clock-output-names : shall be reference name.
+ - #clock-cells : from common clock binding; shall be set to 0.
+ - reg : the mux register address. It should be the offset of the container.
+ - clkgate : bit index to control the clock gate in the gate register.
+
+Optional properties for gate clocks:
+ - clkgate-inverted : it indicates that setting 0 could enable the clock gate
+ and setting 1 could disable the clock gate.
+ - clkgate-seperated-reg : it indicates that there're three continuous
+ registers (enable, disable & status) for the same clock gate.
+
+
+
+Required properties for divider clocks:
+ - compatible : shall be "hisilicon,clk-div".
+ - clocks : shall be the input parent clock phandle for the clock. This should
+ be the reference clock.
+ - clock-output-names : shall be reference name.
+ - reg : the divider register address. It should be the offset of the
+ container.
+ - clkdiv-mask : mask bits of the divider register.
+ - clkdiv-min : the minimum divider of the clock divider.
+ - clkdiv-max : the maximum divider of the clock divider.
+
+Optional properties for divider clocks:
+ - clkdiv-hiword-mask : indicates that the bit[31:16] are the hiword mask
+ of divider selected bits (bit[15:0]). The bit[15:0] is valid only when
+ bit[31:16] is set.
+
+
+
+For example:
+ timer0_mux: timer0_mux@fc802000 {
+ compatible = "hisilicon,clk-mux";
+ #clock-cells = <0>;
+ clocks = <&osc32k &timerclk01>;
+ clock-output-names = "timer0_mux";
+ reg = <0xfc802000 0x4>;
+ clkmux-mask = <0x8000>;
+ clkmux-table = <0 0x8000>;
+ };
+ uart0_mux: uart0_mux@fc802100 {
+ compatible = "hisilicon,clk-mux";
+ #clock-cells = <0>;
+ clocks = <&osc26m &pclk>;
+ clock-output-names = "uart0_mux";
+ reg = <0xfc802100 0x4>;
+ clkmux-mask = <0x80>;
+ /* each item value */
+ clkmux-table = <0 0x80>;
+ clkmux-hiword-mask;
+ };
+ timerclk01: timerclk01@fc802020 {
+ compatible = "hisilicon,clk-gate";
+ #clock-cells = <0>;
+ clocks = <&timer_rclk01>;
+ clock-output-names = "timerclk01";
+ reg = <0xfc802020 0x4>;
+ clkgate = <0>;
+ clkgate-seperated-reg;
+ };
+ mmc1_div: mmc1_div@fc802108 {
+ compatible = "hisilicon,clk-div";
+ #clock-cells = <0>;
+ clocks = <&mmc1_mux>;
+ clock-output-names = "mmc1_div";
+ reg = <0xfc802108 0x4>;
+ clkdiv-mask = <0x1e0>;
+ clkdiv-min = <1>;
+ clkdiv-max = <16>;
+ clkdiv-hiword-mask;
+ };
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o
# SoCs specific
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
+obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
obj-$(CONFIG_ARCH_MXS) += mxs/
new file mode 100644
@@ -0,0 +1,2 @@
+
+obj-y += clk-hi3xxx.o clkgate-seperated.o
new file mode 100644
@@ -0,0 +1,221 @@
+/*
+ * Hisilicon Hi3xxx clock driver
+ *
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ * Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include "clk-hi3xxx.h"
+
+static DEFINE_SPINLOCK(hi3xxx_clk_lock);
+
+static void __init hi3xxx_clkgate_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *clk_name, **parent_names, *name;
+ unsigned long flags = 0;
+ u32 bit_idx;
+ void __iomem *reg;
+
+ reg = of_iomap(np, 0);
+ if (!reg)
+ goto err;
+ if (of_property_read_string(np, "clock-output-names", &clk_name))
+ goto err;
+ if (of_property_read_u32(np, "clkgate", &bit_idx))
+ goto err;
+
+ /* gate only has the fixed parent */
+ parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
+ if (!parent_names)
+ goto err;
+ parent_names[0] = of_clk_get_parent_name(np, 0);
+
+ if (of_property_read_bool(np, "clkgate-seperated-reg")) {
+ clk = hi3xxx_register_clkgate_sep(NULL, clk_name, parent_names[0],
+ 0, reg, (u8)bit_idx, flags,
+ &hi3xxx_clk_lock);
+ } else {
+ if (of_property_read_bool(np, "clkgate-inverted"))
+ flags |= CLK_GATE_SET_TO_DISABLE;
+ clk = clk_register_gate(NULL, clk_name, parent_names[0], 0, reg,
+ (u8)bit_idx, flags, &hi3xxx_clk_lock);
+ }
+ if (IS_ERR(clk))
+ goto err_clk;
+ if (!of_property_read_string(np, "clock-names", &name))
+ clk_register_clkdev(clk, name, NULL);
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+err_clk:
+ kfree(parent_names);
+err:
+ pr_err("Fail on registering hi3xxx clkgate node.\n");
+}
+CLK_OF_DECLARE(hi3xxx_gate, "hisilicon,clk-gate", hi3xxx_clkgate_setup)
+
+static int __init hi3xxx_parse_mux(struct device_node *np,
+ u8 *num_parents,
+ u32 *table)
+{
+ int i, cnt, ret;
+
+ /* get the count of items in mux */
+ cnt = of_count_phandle_with_args(np, "clocks", "#clock-cells");
+ if (cnt < 0) {
+ pr_err("%s: failed to find clock parent\n", __func__);
+ return cnt;
+ }
+
+ for (i = 0; i < cnt; i++) {
+ if (!of_clk_get_parent_name(np, i))
+ return -ENOENT;
+ }
+ *num_parents = cnt;
+ table = kzalloc(sizeof(u32 *) * cnt, GFP_KERNEL);
+ if (!table)
+ return -ENOMEM;
+ ret = of_property_read_u32_array(np, "clkmux-table",
+ table, cnt);
+ if (ret)
+ goto err;
+ return 0;
+err:
+ kfree(table);
+ return ret;
+}
+
+static void __init hi3xxx_clkmux_setup(struct device_node *np)
+{
+ struct clk *clk;
+ const char *clk_name, **parent_names = NULL;
+ u32 mask, *table = NULL;
+ u8 num_parents, shift, clk_mux_flags = 0;
+ void __iomem *reg;
+ int i, ret;
+
+ reg = of_iomap(np, 0);
+ if (!reg)
+ goto err;
+ if (of_property_read_string(np, "clock-output-names", &clk_name))
+ goto err;
+ if (of_property_read_u32(np, "clkmux-mask", &mask))
+ goto err;
+ if (of_property_read_bool(np, "clkmux-hiword-mask"))
+ clk_mux_flags = CLK_MUX_HIWORD_MASK;
+
+ ret = hi3xxx_parse_mux(np, &num_parents, table);
+ if (ret)
+ goto err;
+
+ parent_names = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+ if (!parent_names)
+ goto err_table;
+ for (i = 0; i < num_parents; i++)
+ parent_names[i] = of_clk_get_parent_name(np, i);
+
+ shift = ffs(mask) - 1;
+ mask = mask >> shift;
+ clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents,
+ CLK_SET_RATE_PARENT, reg, shift, mask,
+ clk_mux_flags, table, &hi3xxx_clk_lock);
+ if (IS_ERR(clk))
+ goto err_clk;
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+ return;
+err_clk:
+ kfree(parent_names);
+err_table:
+ kfree(table);
+err:
+ pr_err("Fail on registering hi3xxx clkmux node.\n");
+}
+CLK_OF_DECLARE(hi3xxx_mux, "hisilicon,clk-mux", hi3xxx_clkmux_setup)
+
+static void __init hi3xxx_clkdiv_setup(struct device_node *np, int mode)
+{
+ struct clk *clk;
+ const char *clk_name, **parent_names;
+ struct clk_div_table *table;
+ unsigned int table_num;
+ u32 min, max, mask;
+ u8 shift, width, clk_div_flags = 0;
+ void __iomem *reg;
+ int i;
+
+ reg = of_iomap(np, 0);
+ if (!reg)
+ goto err;
+ if (of_property_read_string(np, "clock-output-names", &clk_name))
+ goto err;
+ if (of_property_read_u32(np, "clkdiv-mask", &mask))
+ goto err;
+ if (of_property_read_u32(np, "clkdiv-min", &min))
+ goto err;
+ if (of_property_read_u32(np, "clkdiv-max", &max))
+ goto err;
+ if (of_property_read_bool(np, "clkdiv-hiword-mask"))
+ clk_div_flags = CLK_DIVIDER_HIWORD_MASK;
+
+ table_num = max - min + 1;
+ table = kzalloc(sizeof(*table) * table_num, GFP_KERNEL);
+ if (!table)
+ goto err;
+
+ for (i = 0; i < table_num; i++) {
+ table[i].div = min + i;
+ table[i].val = table[i].div - 1;
+ }
+
+ /* gate only has the fixed parent */
+ parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
+ if (!parent_names)
+ goto err_par;
+ parent_names[0] = of_clk_get_parent_name(np, 0);
+ shift = ffs(mask) - 1;
+ width = fls(mask) - ffs(mask) + 1;
+ clk = clk_register_divider_table(NULL, clk_name, parent_names[0], 0,
+ reg, shift, width, clk_div_flags,
+ table, &hi3xxx_clk_lock);
+ if (IS_ERR(clk))
+ goto err_clk;
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ return;
+err_clk:
+ kfree(parent_names);
+err_par:
+ kfree(table);
+err:
+ pr_err("Fail on registering hi3xxx clkdiv node\n");
+}
+CLK_OF_DECLARE(hi3xxx_div, "hisilicon,clk-div", hi3xxx_clkdiv_setup)
new file mode 100644
@@ -0,0 +1,34 @@
+/*
+ * Hisilicon Hi3620 clock gate driver
+ *
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ * Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __HI3XXX_CLKGATE_SEPERATED
+#define __HI3XXX_CLKGATE_SEPERATED
+
+extern struct clk *hi3xxx_register_clkgate_sep(struct device *, const char *,
+ const char *, unsigned long,
+ void __iomem *, u8,
+ u8, spinlock_t *);
+
+#endif /* __HI3XXX_CLKGATE_SEPERATED */
new file mode 100644
@@ -0,0 +1,129 @@
+/*
+ * Hisilicon Hi3620 clock gate driver
+ *
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ * Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include "clk-hi3xxx.h"
+
+/* Hi3620 clock gate register offset */
+#define CLKGATE_SEPERATED_ENABLE 0x0
+#define CLKGATE_SEPERATED_DISABLE 0x4
+#define CLKGATE_SEPERATED_STATUS 0x8
+
+struct clkgate_seperated {
+ struct clk_hw hw;
+ void __iomem *enable; /* enable register */
+ u8 bit_idx; /* bits in enable/disable register */
+ u8 flags;
+ spinlock_t *lock;
+};
+
+static int clkgate_seperated_enable(struct clk_hw *hw)
+{
+ struct clkgate_seperated *sclk;
+ unsigned long flags = 0;
+ u32 reg;
+
+ sclk = container_of(hw, struct clkgate_seperated, hw);
+ if (sclk->lock)
+ spin_lock_irqsave(sclk->lock, flags);
+ reg = BIT(sclk->bit_idx);
+ writel_relaxed(reg, sclk->enable);
+ readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+ if (sclk->lock)
+ spin_unlock_irqrestore(sclk->lock, flags);
+ return 0;
+}
+
+static void clkgate_seperated_disable(struct clk_hw *hw)
+{
+ struct clkgate_seperated *sclk;
+ unsigned long flags = 0;
+ u32 reg;
+
+ sclk = container_of(hw, struct clkgate_seperated, hw);
+ if (sclk->lock)
+ spin_lock_irqsave(sclk->lock, flags);
+ reg = BIT(sclk->bit_idx);
+ writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
+ readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+ if (sclk->lock)
+ spin_unlock_irqrestore(sclk->lock, flags);
+}
+
+static int clkgate_seperated_is_enabled(struct clk_hw *hw)
+{
+ struct clkgate_seperated *sclk;
+ u32 reg;
+
+ sclk = container_of(hw, struct clkgate_seperated, hw);
+ reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
+ reg &= BIT(sclk->bit_idx);
+
+ return reg ? 1 : 0;
+}
+
+static struct clk_ops clkgate_seperated_ops = {
+ .enable = clkgate_seperated_enable,
+ .disable = clkgate_seperated_disable,
+ .is_enabled = clkgate_seperated_is_enabled,
+};
+
+struct clk *hi3xxx_register_clkgate_sep(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+ struct clkgate_seperated *sclk;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ sclk = kzalloc(sizeof(struct clkgate_seperated), GFP_KERNEL);
+ if (!sclk) {
+ pr_err("%s: fail to allocate seperated gated clk\n", __func__);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = name;
+ init.ops = &clkgate_seperated_ops;
+ init.flags = flags | CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ sclk->enable = reg + CLKGATE_SEPERATED_ENABLE;
+ sclk->bit_idx = bit_idx;
+ sclk->flags = clk_gate_flags;
+ sclk->hw.init = &init;
+
+ clk = clk_register(dev, &sclk->hw);
+ if (IS_ERR(clk))
+ kfree(sclk);
+ return clk;
+}
Add clock support with device tree on Hisilicon SoC. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> --- .../devicetree/bindings/clock/hisilicon.txt | 99 +++++++++ drivers/clk/Makefile | 1 + drivers/clk/hisilicon/Makefile | 2 + drivers/clk/hisilicon/clk-hi3xxx.c | 221 +++++++++++++++++++++ drivers/clk/hisilicon/clk-hi3xxx.h | 34 ++++ drivers/clk/hisilicon/clkgate-seperated.c | 129 ++++++++++++ 6 files changed, 486 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hisilicon.txt create mode 100644 drivers/clk/hisilicon/Makefile create mode 100644 drivers/clk/hisilicon/clk-hi3xxx.c create mode 100644 drivers/clk/hisilicon/clk-hi3xxx.h create mode 100644 drivers/clk/hisilicon/clkgate-seperated.c