diff mbox

[1/2] radeon: fix mipmap level 0 and 1 alignment for SI and CIK

Message ID 1384538127-11532-1-git-send-email-maraeo@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Marek Olšák Nov. 15, 2013, 5:55 p.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 radeon/radeon_surface.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

Comments

Michel Dänzer Nov. 18, 2013, 9:29 a.m. UTC | #1 
On Fre, 2013-11-15 at 18:55 +0100, Marek Olšák wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
> 
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>

[...]

> @@ -1657,10 +1659,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
>                  tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
>                  break;
>              case SI_TILE_MODE_DEPTH_STENCIL_2D:
> -                if (surf_man->family >= CHIP_BONAIRE)
> -                    tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
> -                else
> -                    tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
> +                tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>                  break;
>              default:
>                  return -EINVAL;

This hunk should be in patch 2.


Other than that, the series is

Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>

However, patch 2 also depends on the corresponding kernel support, which
I just submitted.


Thanks for ironing out the kinks of this, Marek!
Marek Olšák Nov. 23, 2013, 12:32 a.m. UTC | #2 
Sorry, the autorship of the other patch changed when I moved the hunk
there and didn't notice it. :(

Marek

On Mon, Nov 18, 2013 at 10:29 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On Fre, 2013-11-15 at 18:55 +0100, Marek Olšák wrote:
>> From: Michel Dänzer <michel.daenzer@amd.com>
>>
>> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
>
> [...]
>
>> @@ -1657,10 +1659,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
>>                  tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
>>                  break;
>>              case SI_TILE_MODE_DEPTH_STENCIL_2D:
>> -                if (surf_man->family >= CHIP_BONAIRE)
>> -                    tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
>> -                else
>> -                    tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>> +                tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>>                  break;
>>              default:
>>                  return -EINVAL;
>
> This hunk should be in patch 2.
>
>
> Other than that, the series is
>
> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
>
> However, patch 2 also depends on the corresponding kernel support, which
> I just submitted.
>
>
> Thanks for ironing out the kinks of this, Marek!
>
>
> --
> Earthling Michel Dänzer            |                  http://www.amd.com
> Libre software enthusiast          |                Mesa and X developer
>
Michel Dänzer Nov. 23, 2013, 6:24 a.m. UTC | #3 
On Sam, 2013-11-23 at 01:32 +0100, Marek Olšák wrote:
> Sorry, the autorship of the other patch changed when I moved the hunk
> there and didn't notice it. :(

No worries.
diff mbox

Patch

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index d5c45c4..56e2e4a 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -1540,6 +1540,7 @@  static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
                               uint64_t offset, unsigned start_level)
 {
     uint32_t xalign, yalign, zalign, slice_align;
+    unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
     unsigned i;
 
     /* compute alignment */
@@ -1551,11 +1552,11 @@  static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
         xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
     }
 
-    if (!start_level) {
-        surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
+    if (start_level <= 1) {
+        surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
 
         if (offset) {
-            offset = ALIGN(offset, surf->bo_alignment);
+            offset = ALIGN(offset, alignment);
         }
     }
 
@@ -1566,7 +1567,7 @@  static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
         /* level0 and first mipmap need to have alignment */
         offset = surf->bo_size;
         if ((i == 0)) {
-            offset = ALIGN(offset, surf->bo_alignment);
+            offset = ALIGN(offset, alignment);
         }
         if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
             if (surf->level == level) {
@@ -1608,6 +1609,7 @@  static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
                               uint64_t offset,
                               unsigned start_level)
 {
+    uint64_t aligned_offset = offset;
     unsigned tilew, tileh, tileb;
     unsigned mtilew, mtileh, mtileb;
     unsigned slice_pt;
@@ -1631,19 +1633,19 @@  static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
     /* macro tile bytes */
     mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
 
-    if (!start_level) {
+    if (start_level <= 1) {
         unsigned alignment = MAX2(256, mtileb);
         surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
 
-        if (offset) {
-            offset = ALIGN(offset, alignment);
+        if (aligned_offset) {
+            aligned_offset = ALIGN(aligned_offset, alignment);
         }
     }
 
     /* build mipmap tree */
     for (i = start_level; i <= surf->last_level; i++) {
         level[i].mode = RADEON_SURF_MODE_2D;
-        si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, offset);
+        si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
         if (level[i].mode == RADEON_SURF_MODE_1D) {
             switch (tile_mode) {
             case SI_TILE_MODE_COLOR_2D_8BPP:
@@ -1657,10 +1659,7 @@  static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
                 tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
                 break;
             case SI_TILE_MODE_DEPTH_STENCIL_2D:
-                if (surf_man->family >= CHIP_BONAIRE)
-                    tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
-                else
-                    tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
+                tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
                 break;
             default:
                 return -EINVAL;
@@ -1668,9 +1667,9 @@  static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
             return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
         }
         /* level0 and first mipmap need to have alignment */
-        offset = surf->bo_size;
+        aligned_offset = surf->bo_size;
         if ((i == 0)) {
-            offset = ALIGN(offset, surf->bo_alignment);
+            aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
         }
         if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
             if (surf->level == level) {