| Message ID | 1386241070-4350-3-git-send-email-ldewangan@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12/05/2013 03:57 AM, Laxman Dewangan wrote: > The tegra124 pinmux controller is identical to tegra114 with > removing some of existing pins from T114 and adding new pins. I already sent this patch. > diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi > + pinmux: pinmux { Note that the rules for DT node naming have changed recently. Node name must include a unit address if the node includes a reg property, and not include a unit address otherwise. So, that should be: + pinmux: pinmux@70000868 { The patch I sent already does that.
On 12/05/2013 04:16 PM, Stephen Warren wrote: > On 12/05/2013 03:57 AM, Laxman Dewangan wrote: >> The tegra124 pinmux controller is identical to tegra114 with >> removing some of existing pins from T114 and adding new pins. > > I already sent this patch. Oh, I do notice one difference between the two patches: Mine: > + reg = <0x70000868 0x148>, /* Pad control registers */ > + <0x70003000 0x40c>; /* Mux registers */ Yours: > + reg = <0x70000868 0x164 /* Pad control registers */ > + 0x70003000 0x434>; /* PinMux registers */ Are the increase register lengths in your patch correct? If so, I guess I'll drop my patch and replace it with yours if you fix up the unit address.
On Friday 06 December 2013 04:49 AM, Stephen Warren wrote: > On 12/05/2013 04:16 PM, Stephen Warren wrote: >> On 12/05/2013 03:57 AM, Laxman Dewangan wrote: >>> The tegra124 pinmux controller is identical to tegra114 with >>> removing some of existing pins from T114 and adding new pins. >> I already sent this patch. > Oh, I do notice one difference between the two patches: > > Mine: > >> + reg = <0x70000868 0x148>, /* Pad control registers */ >> + <0x70003000 0x40c>; /* Mux registers */ > Yours: > >> + reg = <0x70000868 0x164 /* Pad control registers */ >> + 0x70003000 0x434>; /* PinMux registers */ > Are the increase register lengths in your patch correct? If so, I guess > I'll drop my patch and replace it with yours if you fix up the unit address. Yes, the last entry of the bank 0 and 1 are: DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), and PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, DP, 0x3430, N, N, N),
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b741300..39bfcce 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -47,6 +47,12 @@ interrupt-controller; }; + pinmux: pinmux { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x70000868 0x164 /* Pad control registers */ + 0x70003000 0x434>; /* PinMux registers */ + }; + /* * There are two serial driver i.e. 8250 based simple serial * driver and APB DMA based serial driver for higher baudrate
The tegra124 pinmux controller is identical to tegra114 with removing some of existing pins from T114 and adding new pins. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- arch/arm/boot/dts/tegra124.dtsi | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)