| Message ID | 1386660576-1861-1-git-send-email-kenneth@whitecape.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Dec 09, 2013 at 11:29:35PM -0800, Kenneth Graunke wrote: > We don't want depth/stencil fast clears or HiZ resolves; we want normal > drawing. Without this, the pixel pipeline doesn't work. > > Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > Cc: Ben Widawsky <ben@bwidawsk.net> > Cc: Damien Lespiau <damien.lespiau@intel.com> Both patches reviewed and pushed, thanks a lot for doing this. Does it mean rendercopy run for you now? (I don't have silicon to test myself). I've also taught my command parser to warn harder about instruction lengths, it was missing the cases you fixed.
On 12/10/2013 03:40 AM, Damien Lespiau wrote: > On Mon, Dec 09, 2013 at 11:29:35PM -0800, Kenneth Graunke wrote: >> We don't want depth/stencil fast clears or HiZ resolves; we want normal >> drawing. Without this, the pixel pipeline doesn't work. >> >> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> >> Cc: Ben Widawsky <ben@bwidawsk.net> >> Cc: Damien Lespiau <damien.lespiau@intel.com> > > Both patches reviewed and pushed, thanks a lot for doing this. Does it > mean rendercopy run for you now? (I don't have silicon to test myself). > > I've also taught my command parser to warn harder about instruction > lengths, it was missing the cases you fixed. It still hangs for me. I also tried Haihao's patch, though I guess I didn't try both together... --Ken
On Tue, 2013-12-10 at 09:04 -0800, Kenneth Graunke wrote: > On 12/10/2013 03:40 AM, Damien Lespiau wrote: > > On Mon, Dec 09, 2013 at 11:29:35PM -0800, Kenneth Graunke wrote: > >> We don't want depth/stencil fast clears or HiZ resolves; we want normal > >> drawing. Without this, the pixel pipeline doesn't work. > >> > >> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> > >> Cc: Ben Widawsky <ben@bwidawsk.net> > >> Cc: Damien Lespiau <damien.lespiau@intel.com> > > > > Both patches reviewed and pushed, thanks a lot for doing this. Does it > > mean rendercopy run for you now? (I don't have silicon to test myself). > > > > I've also taught my command parser to warn harder about instruction > > lengths, it was missing the cases you fixed. > > It still hangs for me. I also tried Haihao's patch, though I guess I > didn't try both together... Now gem_render_copy works fine for me without my workaround. Thanks Haihao > > --Ken > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/lib/gen8_render.h b/lib/gen8_render.h index 7b89876..ca53d64 100644 --- a/lib/gen8_render.h +++ b/lib/gen8_render.h @@ -22,6 +22,8 @@ # define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) # define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16 (4 << 1) +#define GEN8_3DSTATE_WM_HZ_OP GEN6_3D(3, 0, 0x52) + #define GEN8_3DSTATE_VF_INSTANCING GEN6_3D(3, 0, 0x49) #define GEN7_3DSTATE_GS GEN6_3D(3, 0, 0x11) #define GEN7_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16) diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index 1a137dd..38dc0e7 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -679,7 +679,17 @@ gen8_emit_ds(struct intel_batchbuffer *batch) { } static void +gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) { + OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void gen8_emit_null_state(struct intel_batchbuffer *batch) { + gen8_emit_wm_hz_op(batch); gen8_emit_hs(batch); OUT_BATCH(GEN7_3DSTATE_TE | (4-2)); OUT_BATCH(0);
We don't want depth/stencil fast clears or HiZ resolves; we want normal drawing. Without this, the pixel pipeline doesn't work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Damien Lespiau <damien.lespiau@intel.com> --- lib/gen8_render.h | 2 ++ lib/rendercopy_gen8.c | 10 ++++++++++ 2 files changed, 12 insertions(+)