| Message ID | 1386897825-6130-4-git-send-email-peter.chen@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 13, 2013 at 09:23:33AM +0800, Peter Chen wrote: > With the auto setting, the PHY's clock and power can be > recovered correctly from low power mode, it is ganranteed by IC logic. s/ganranteed/guaranteed Also, I think you need to be slightly more verbose here. Maybe explain a bit what is the "auto setting". From what I can see from the code, it's a way to let HW manage clock gating. Another question, does this feature work in all SoCs where this IP is available ? cheers
On Fri, Dec 13, 2013 at 12:23 PM, Felipe Balbi <balbi@ti.com> wrote: > On Fri, Dec 13, 2013 at 09:23:33AM +0800, Peter Chen wrote: >> With the auto setting, the PHY's clock and power can be >> recovered correctly from low power mode, it is ganranteed by IC logic. > > s/ganranteed/guaranteed > Will change. > Also, I think you need to be slightly more verbose here. Maybe explain a > bit what is the "auto setting". From what I can see from the code, it's > a way to let HW manage clock gating. > Yes, you are right. This feature is used to open related power and clocks automatically after receiving wakeup signal. I will add more explanation. > Another question, does this feature work in all SoCs where this IP is > available ? > Yes, these auto bits are existed from the 1st generation mxs-phy.
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index 6d49040..0c6f3bc 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -31,6 +31,11 @@ #define BM_USBPHY_CTRL_SFTRST BIT(31) #define BM_USBPHY_CTRL_CLKGATE BIT(30) +#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) +#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) +#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) +#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) +#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) @@ -96,9 +101,18 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) /* Power up the PHY */ writel(0, base + HW_USBPHY_PWD); - /* enable FS/LS device */ - writel(BM_USBPHY_CTRL_ENUTMILEVEL2 | - BM_USBPHY_CTRL_ENUTMILEVEL3, + /* + * USB PHY Ctrl Setting + * - Auto clock/power on + * - Enable full/low speed support + */ + writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | + BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | + BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | + BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | + BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | + BM_USBPHY_CTRL_ENUTMILEVEL2 | + BM_USBPHY_CTRL_ENUTMILEVEL3, base + HW_USBPHY_CTRL_SET); return 0;
With the auto setting, the PHY's clock and power can be recovered correctly from low power mode, it is ganranteed by IC logic. Signed-off-by: Peter Chen <peter.chen@freescale.com> --- drivers/usb/phy/phy-mxs-usb.c | 20 +++++++++++++++++--- 1 files changed, 17 insertions(+), 3 deletions(-)