| Message ID | 1387297337-25493-3-git-send-email-ivan.khoronzhuk@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tuesday 17 December 2013 11:22 AM, Ivan Khoronzhuk wrote: > This patch provides bindings for the 64-bit timer in the KeyStone > architecture devices. The timer can be configured as a general-purpose 64-bit > timer, dual general-purpose 32-bit timers. When configured as dual 32-bit > timers, each half can operate in conjunction (chain mode) or independently > (unchained mode) of each other. > > It is global timer is a free running up-counter and can generate interrupt > when the counter reaches preset counter values. > > Documentation: > http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf > > Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> > --- Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt new file mode 100644 index 0000000..5fbe361 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt @@ -0,0 +1,29 @@ +* Device tree bindings for Texas instruments Keystone timer + +This document provides bindings for the 64-bit timer in the KeyStone +architecture devices. The timer can be configured as a general-purpose 64-bit +timer, dual general-purpose 32-bit timers. When configured as dual 32-bit +timers, each half can operate in conjunction (chain mode) or independently +(unchained mode) of each other. + +It is global timer is a free running up-counter and can generate interrupt +when the counter reaches preset counter values. + +Documentation: +http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf + +Required properties: + +- compatible : should be "ti,keystone-timer". +- reg : specifies base physical address and count of the registers. +- interrupts : interrupt generated by the timer. +- clocks : the clock feeding the timer clock. + +Example: + +timer@22f0000 { + compatible = "ti,keystone-timer"; + reg = <0x022f0000 0x80>; + interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; + clocks = <&clktimer15>; +};
This patch provides bindings for the 64-bit timer in the KeyStone architecture devices. The timer can be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers. When configured as dual 32-bit timers, each half can operate in conjunction (chain mode) or independently (unchained mode) of each other. It is global timer is a free running up-counter and can generate interrupt when the counter reaches preset counter values. Documentation: http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> --- .../bindings/timer/ti,keystone-timer.txt | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/ti,keystone-timer.txt