| Message ID | 1387258107-19232-6-git-send-email-vandana.kannan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote: > For Broadwell, there is one instance of Transcoder MN values per transcoder. > For dynamic switching between multiple refreshr rates, M/N values may be > reprogrammed on the fly. Link N programming triggers update of all data and > link M & N registers and the new M/N values will be used in the next frame > that is output. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++---- > 1 file changed, 19 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 209be3c..183cfd7 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > struct drm_i915_private *dev_priv = dev->dev_private; > enum transcoder transcoder = crtc->config.cpu_transcoder; > > - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { > + if (INTEL_INFO(dev)->gen >= 8) { > + I915_WRITE(PIPE_DATA_M1(transcoder), > + TU_SIZE(m_n->tu) | m_n->gmch_m); > + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); > + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); > + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); > + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { Ouch. Double ouch later. -Chris
On Dec-17-2013 6:00 PM, Chris Wilson wrote: > On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote: >> For Broadwell, there is one instance of Transcoder MN values per transcoder. >> For dynamic switching between multiple refreshr rates, M/N values may be >> reprogrammed on the fly. Link N programming triggers update of all data and >> link M & N registers and the new M/N values will be used in the next frame >> that is output. >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> >> --- >> drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++---- >> 1 file changed, 19 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 209be3c..183cfd7 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >> struct drm_i915_private *dev_priv = dev->dev_private; >> enum transcoder transcoder = crtc->config.cpu_transcoder; >> >> - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { >> + if (INTEL_INFO(dev)->gen >= 8) { >> + I915_WRITE(PIPE_DATA_M1(transcoder), >> + TU_SIZE(m_n->tu) | m_n->gmch_m); >> + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); >> + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); >> + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); >> + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { > > Ouch. Double ouch later. > -Chris > We are looking to write in M1/N1 registers for BDW and M2/N2 registers for HSW and below. What is your suggestion on how to implement this ?
On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote: > On Dec-17-2013 6:00 PM, Chris Wilson wrote: > > On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote: > >> For Broadwell, there is one instance of Transcoder MN values per transcoder. > >> For dynamic switching between multiple refreshr rates, M/N values may be > >> reprogrammed on the fly. Link N programming triggers update of all data and > >> link M & N registers and the new M/N values will be used in the next frame > >> that is output. > >> > >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > >> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> > >> --- > >> drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++---- > >> 1 file changed, 19 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >> index 209be3c..183cfd7 100644 > >> --- a/drivers/gpu/drm/i915/intel_dp.c > >> +++ b/drivers/gpu/drm/i915/intel_dp.c > >> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > >> struct drm_i915_private *dev_priv = dev->dev_private; > >> enum transcoder transcoder = crtc->config.cpu_transcoder; > >> > >> - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { > >> + if (INTEL_INFO(dev)->gen >= 8) { > >> + I915_WRITE(PIPE_DATA_M1(transcoder), > >> + TU_SIZE(m_n->tu) | m_n->gmch_m); > >> + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); > >> + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); > >> + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); > >> + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { > > > > Ouch. Double ouch later. > > -Chris > > > We are looking to write in M1/N1 registers for BDW and M2/N2 registers > for HSW and below. What is your suggestion on how to implement this ? if (gen >= 8) { } else if (gen >= 5) { } Or as you use gen >= 5 && gen < 8 elsewhere, a feature macro would be even more sensible, HAS_DRRS(). -Chris
On Dec-18-2013 2:31 PM, Chris Wilson wrote: > On Wed, Dec 18, 2013 at 01:54:56PM +0530, Vandana Kannan wrote: >> On Dec-17-2013 6:00 PM, Chris Wilson wrote: >>> On Tue, Dec 17, 2013 at 10:58:27AM +0530, Vandana Kannan wrote: >>>> For Broadwell, there is one instance of Transcoder MN values per transcoder. >>>> For dynamic switching between multiple refreshr rates, M/N values may be >>>> reprogrammed on the fly. Link N programming triggers update of all data and >>>> link M & N registers and the new M/N values will be used in the next frame >>>> that is output. >>>> >>>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >>>> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> >>>> --- >>>> drivers/gpu/drm/i915/intel_dp.c | 23 +++++++++++++++++++---- >>>> 1 file changed, 19 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >>>> index 209be3c..183cfd7 100644 >>>> --- a/drivers/gpu/drm/i915/intel_dp.c >>>> +++ b/drivers/gpu/drm/i915/intel_dp.c >>>> @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) >>>> struct drm_i915_private *dev_priv = dev->dev_private; >>>> enum transcoder transcoder = crtc->config.cpu_transcoder; >>>> >>>> - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { >>>> + if (INTEL_INFO(dev)->gen >= 8) { >>>> + I915_WRITE(PIPE_DATA_M1(transcoder), >>>> + TU_SIZE(m_n->tu) | m_n->gmch_m); >>>> + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); >>>> + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); >>>> + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); >>>> + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { >>> >>> Ouch. Double ouch later. >>> -Chris >>> >> We are looking to write in M1/N1 registers for BDW and M2/N2 registers >> for HSW and below. What is your suggestion on how to implement this ? > > if (gen >= 8) { > } else if (gen >= 5) { > } > > Or as you use gen >= 5 && gen < 8 elsewhere, a feature macro would be > even more sensible, HAS_DRRS(). > -Chris > I will make this change to if (gen >= 8) { } else if (gen >= 5) { } - Vandana
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 209be3c..183cfd7 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -798,9 +798,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) struct drm_i915_private *dev_priv = dev->dev_private; enum transcoder transcoder = crtc->config.cpu_transcoder; - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { + if (INTEL_INFO(dev)->gen >= 8) { + I915_WRITE(PIPE_DATA_M1(transcoder), + TU_SIZE(m_n->tu) | m_n->gmch_m); + I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); + I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); + I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m_n->tu) | m_n->gmch_m); + TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); @@ -3617,8 +3623,17 @@ intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) mutex_lock(&intel_dp->drrs_state.mutex); - /* Haswell and below */ - if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { + if (INTEL_INFO(dev)->gen >= 8) { + switch (index) { + case DRRS_HIGH_RR: + intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n); + break; + case DRRS_LOW_RR: + intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); + break; + }; + } else if (INTEL_INFO(dev)->gen >= 5 && INTEL_INFO(dev)->gen < 8) { + /* Haswell and below */ reg = PIPECONF(intel_crtc->config.cpu_transcoder); val = I915_READ(reg); if (index > DRRS_HIGH_RR) {