diff mbox

[v5,3/4] ARM: BCM5301X: add dts files for BCM4708 SoC

Message ID 1388965601-18329-4-git-send-email-hauke@hauke-m.de (mailing list archive)
State New, archived
Headers show

Commit Message

Hauke Mehrtens Jan. 5, 2014, 11:46 p.m. UTC 
This uses the newly added BCM5301X SoC code.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/Makefile                  |    1 +
 arch/arm/boot/dts/bcm4708-netgear-r6250.dts |   20 ++++++
 arch/arm/boot/dts/bcm4708.dtsi              |  102 +++++++++++++++++++++++++++
 3 files changed, 123 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm4708-netgear-r6250.dts
 create mode 100644 arch/arm/boot/dts/bcm4708.dtsi

Comments

Thomas Petazzoni Jan. 6, 2014, 1 a.m. UTC | #1 
Dear Hauke Mehrtens,

On Mon,  6 Jan 2014 00:46:40 +0100, Hauke Mehrtens wrote:

> +	uart@18000300 {
> +		compatible = "ns16550";
> +		reg = <0x18000300 0x100>;
> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	uart@18000400 {
> +		compatible = "ns16550";
> +		reg = <0x18000400 0x100>;
> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-frequency = <100000000>;
> +	};
> +
> +	scu@19020000 {
> +		compatible = "arm,cortex-a9-scu";
> +		reg = <0x19020000 0x100>;
> +	};
> +
> +	timer@19020200 {
> +		compatible = "arm,cortex-a9-global-timer";
> +		reg = <0x19020200 0x100>;
> +		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk_periph>;
> +	};
> +
> +	local-timer@19020600 {
> +		compatible = "arm,cortex-a9-twd-timer";
> +		reg = <0x19020600 0x100>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk_periph>;
> +	};
> +
> +	gic: interrupt-controller@19021000 {
> +		compatible = "arm,cortex-a9-gic";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0x19021000 0x1000>,
> +		      <0x19020100 0x100>;
> +	};
> +
> +	L2: cache-controller@19022000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0x19022000 0x1000>;
> +		cache-unified;
> +		cache-level = <2>;
> +	};

I don't know if that has been discussed before, but most of the DTS
group the internal SoC peripherals in some top-level node that
represents the internal bus (or busses) of the SoC, like:

	<some bus name> {
		uart@... {
			...
		};

		gic@... {
			...
		};
	};

This allows to have the in-SoC peripherals cleanly separated from other
things in the DTS. It would also you to use a ranges = <...> property
to do an address translation on this bus, and replace the absolute
addresses for each of the peripherals by offsets relative to the base
address of where all peripherals are mapped.

That said, having this top-level node is most likely not a requirement,
so my comment is mainly meant to open the discussion. I'm sure Arnd
will give his opinion on this :)

Best regards,

Thomas
Hauke Mehrtens Jan. 6, 2014, 9:17 p.m. UTC | #2 
On 01/06/2014 02:00 AM, Thomas Petazzoni wrote:
> Dear Hauke Mehrtens,
> 
> On Mon,  6 Jan 2014 00:46:40 +0100, Hauke Mehrtens wrote:
> 
>> +	uart@18000300 {
>> +		compatible = "ns16550";
>> +		reg = <0x18000300 0x100>;
>> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +		clock-frequency = <100000000>;
>> +	};
>> +
>> +	uart@18000400 {
>> +		compatible = "ns16550";
>> +		reg = <0x18000400 0x100>;
>> +		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +		clock-frequency = <100000000>;
>> +	};
>> +
>> +	scu@19020000 {
>> +		compatible = "arm,cortex-a9-scu";
>> +		reg = <0x19020000 0x100>;
>> +	};
>> +
>> +	timer@19020200 {
>> +		compatible = "arm,cortex-a9-global-timer";
>> +		reg = <0x19020200 0x100>;
>> +		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&clk_periph>;
>> +	};
>> +
>> +	local-timer@19020600 {
>> +		compatible = "arm,cortex-a9-twd-timer";
>> +		reg = <0x19020600 0x100>;
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&clk_periph>;
>> +	};
>> +
>> +	gic: interrupt-controller@19021000 {
>> +		compatible = "arm,cortex-a9-gic";
>> +		#interrupt-cells = <3>;
>> +		#address-cells = <0>;
>> +		interrupt-controller;
>> +		reg = <0x19021000 0x1000>,
>> +		      <0x19020100 0x100>;
>> +	};
>> +
>> +	L2: cache-controller@19022000 {
>> +		compatible = "arm,pl310-cache";
>> +		reg = <0x19022000 0x1000>;
>> +		cache-unified;
>> +		cache-level = <2>;
>> +	};
> 
> I don't know if that has been discussed before, but most of the DTS
> group the internal SoC peripherals in some top-level node that
> represents the internal bus (or busses) of the SoC, like:
> 
> 	<some bus name> {
> 		uart@... {
> 			...
> 		};
> 
> 		gic@... {
> 			...
> 		};
> 	};
> 
> This allows to have the in-SoC peripherals cleanly separated from other
> things in the DTS. It would also you to use a ranges = <...> property
> to do an address translation on this bus, and replace the absolute
> addresses for each of the peripherals by offsets relative to the base
> address of where all peripherals are mapped.
> 
> That said, having this top-level node is most likely not a requirement,
> so my comment is mainly meant to open the discussion. I'm sure Arnd
> will give his opinion on this :)
> 

I spited it up like it was done for the rockchip SoCs.
One dtsi file for a line of SoCs, one for the specific SoC and one for
the device. How does this ranges stuff work, do you have an example for me?

Hauke
Arnd Bergmann Jan. 7, 2014, 4:22 p.m. UTC | #3 
On Monday 06 January 2014, Hauke Mehrtens wrote:
> On 01/06/2014 02:00 AM, Thomas Petazzoni wrote:

> > I don't know if that has been discussed before, but most of the DTS
> > group the internal SoC peripherals in some top-level node that
> > represents the internal bus (or busses) of the SoC, like:
> > 
> > 	<some bus name> {
> > 		uart@... {
> > 			...
> > 		};
> > 
> > 		gic@... {
> > 			...
> > 		};
> > 	};
> > 
> > This allows to have the in-SoC peripherals cleanly separated from other
> > things in the DTS. It would also you to use a ranges = <...> property
> > to do an address translation on this bus, and replace the absolute
> > addresses for each of the peripherals by offsets relative to the base
> > address of where all peripherals are mapped.
> > 
> > That said, having this top-level node is most likely not a requirement,
> > so my comment is mainly meant to open the discussion. I'm sure Arnd
> > will give his opinion on this :)
> > 
> 
> I spited it up like it was done for the rockchip SoCs.
> One dtsi file for a line of SoCs, one for the specific SoC and one for
> the device. How does this ranges stuff work, do you have an example for me?

kirkwood.dtsi has some good examples. For instance there is a UART at
0xf1012000, which gets described as a device at local address 0x12000,
and a parent bus that translates the global 1MB range at 0xf1000000 to
local address range 0x00000000. The organization of the buses should
match the physical layout of the chip as described in the data sheet.

Note that in case of kirkwood, the 1MB register range is actually
relocatable and the devices are described using offsets in the data
sheet. On other SoCs the internal bus still uses a full 32-bit
address. It still makes sense to split up the device nodes by buses
then, but the you may want a ranges property like 

	ranges = <0x190000000 0x19000000 0x01000000>;

rather than 

	ranges = <0 0x19000000 0x01000000>;

in that case, so the addresses in the device nodes still match
the numbers from the data sheet. You can also have an empty "ranges"
property that just states that all addresses are available on the
bus, if that is what the hardware does.

	Arnd
diff mbox

Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..9c385bb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -45,6 +45,7 @@  dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
 	bcm28155-ap.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
 	da850-evm.dtb
 dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
new file mode 100644
index 0000000..34875f6
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -0,0 +1,20 @@ 
+/*
+ * Broadcom BCM470X / BCM5301X arm platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+
+/ {
+	compatible = "netgear,r6250v1", "brcm,bcm4708";
+	model = "Netgear R6250 V1 (BCM4708)";
+
+	memory {
+		reg = <0x00000000 0x08000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
new file mode 100644
index 0000000..36937f1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -0,0 +1,102 @@ 
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm4708";
+	model = "Broadcom BCM4708";
+	interrupt-parent = <&gic>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* As long as we do not have a real clock driver us this
+		 * fixed clock */
+		clk_periph: periph {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <400000000>;
+		};
+	};
+
+	uart@18000300 {
+		compatible = "ns16550";
+		reg = <0x18000300 0x100>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+	};
+
+	uart@18000400 {
+		compatible = "ns16550";
+		reg = <0x18000400 0x100>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+	};
+
+	scu@19020000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0x19020000 0x100>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_periph>;
+	};
+
+	local-timer@19020600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0x19020600 0x100>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_periph>;
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: cache-controller@19022000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+};