| Message ID | 20131219124929.3226.79335.stgit@tamien (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12/19/2013 05:49 AM, Paul Walmsley wrote: > Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect > the DFLL (and FCPU cluster) voltage regulator. > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt > +NVIDIA Tegra114 DFLL clocksource data in the board DTS file > + > +Optional properties: > + > +- status : device availability -- managed by the DT integration code, not > + the DFLL driver. Should be set to "okay" if the DFLL is to be > + used on this board type. There's certainly no need to document the same DT property twice. The DT docs are about documenting the schema. If the DT author decides to split the properties between a .dtsi and a .dts file, that's irrelevant to the schema.
On Thu, 19 Dec 2013, Stephen Warren wrote: > On 12/19/2013 05:49 AM, Paul Walmsley wrote: >> Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect >> the DFLL (and FCPU cluster) voltage regulator. > >> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt > >> +NVIDIA Tegra114 DFLL clocksource data in the board DTS file >> + >> +Optional properties: >> + >> +- status : device availability -- managed by the DT integration code, not >> + the DFLL driver. Should be set to "okay" if the DFLL is to be >> + used on this board type. > > There's certainly no need to document the same DT property twice. I've just dropped this section, per your earlier suggestion. - Paul
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt index b868bf97bc3d..c4072b3f16fc 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt @@ -41,3 +41,19 @@ dfll@70110000 { status = "disabled"; }; +... + +NVIDIA Tegra114 DFLL clocksource data in the board DTS file + +Optional properties: + +- status : device availability -- managed by the DT integration code, not + the DFLL driver. Should be set to "okay" if the DFLL is to be + used on this board type. + + +Example: + +dfll@70110000 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 88be40cf8845..2e8e7ae60c1a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1063,6 +1063,10 @@ }; }; + dfll@70110000 { + status = "okay"; + }; + sdhci@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; bus-width = <4>;
Expose the DFLL device on the NVIDIA Tegra114 Dalmore board, and connect the DFLL (and FCPU cluster) voltage regulator. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> --- .../bindings/clock/nvidia,tegra114-dfll.txt | 16 ++++++++++++++++ arch/arm/boot/dts/tegra114-dalmore.dts | 4 ++++ 2 files changed, 20 insertions(+)