| Message ID | 1390886974-2530-1-git-send-email-olvaffe@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu <olvaffe@gmail.com> wrote: > From: Chia-I Wu <olv@lunarg.com> > > The optimization is available on Ivy Bridge and later, and is disabled by > default. Enabling it helps certain workloads such as GLBenchmark TRex test. > > No piglit regression. > > v2 > - no need to save the register before suspend as init_clock_gating can > correctly program it after resume > - split IVB change to another commit > > Signed-off-by: Chia-I Wu <olv@lunarg.com> What about byt? -Daniel
On Wed, Jan 29, 2014 at 9:56 AM, Daniel Vetter <daniel@ffwll.ch> wrote: > On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu <olvaffe@gmail.com> wrote: >> From: Chia-I Wu <olv@lunarg.com> >> >> The optimization is available on Ivy Bridge and later, and is disabled by >> default. Enabling it helps certain workloads such as GLBenchmark TRex test. >> >> No piglit regression. >> >> v2 >> - no need to save the register before suspend as init_clock_gating can >> correctly program it after resume >> - split IVB change to another commit >> >> Signed-off-by: Chia-I Wu <olv@lunarg.com> > > What about byt? > -Daniel In the previous thread, Ville pointed out that the documentation doesn't say anything about BYT for this bit, so it's unknown whether it's supported, and Chia-I said > Though I will leave BDW/VLV out as I do not have the hardware. I do have BYT, so I'll check it out, but this patch can go in without it that information, since Chia-I took Ville's advice and split the patches into per-generation hunks.
On Wed, Jan 29, 2014 at 06:23:40PM -0800, Matt Turner wrote: > On Wed, Jan 29, 2014 at 9:56 AM, Daniel Vetter <daniel@ffwll.ch> wrote: > > On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu <olvaffe@gmail.com> wrote: > >> From: Chia-I Wu <olv@lunarg.com> > >> > >> The optimization is available on Ivy Bridge and later, and is disabled by > >> default. Enabling it helps certain workloads such as GLBenchmark TRex test. > >> > >> No piglit regression. > >> > >> v2 > >> - no need to save the register before suspend as init_clock_gating can > >> correctly program it after resume > >> - split IVB change to another commit > >> > >> Signed-off-by: Chia-I Wu <olv@lunarg.com> > > > > What about byt? > > -Daniel > > In the previous thread, Ville pointed out that the documentation > doesn't say anything about BYT for this bit, so it's unknown whether > it's supported, and Chia-I said > > > Though I will leave BDW/VLV out as I do not have the hardware. > > I do have BYT, so I'll check it out, but this patch can go in without > it that information, since Chia-I took Ville's advice and split the > patches into per-generation hunks. Make sense. Patches merged and I'll happily pull in the byt update if that one checks out ok. -Daniel
On Thu, Jan 30, 2014 at 01:10:07PM +0100, Daniel Vetter wrote: > On Wed, Jan 29, 2014 at 06:23:40PM -0800, Matt Turner wrote: > > On Wed, Jan 29, 2014 at 9:56 AM, Daniel Vetter <daniel@ffwll.ch> wrote: > > > On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu <olvaffe@gmail.com> wrote: > > >> From: Chia-I Wu <olv@lunarg.com> > > >> > > >> The optimization is available on Ivy Bridge and later, and is disabled by > > >> default. Enabling it helps certain workloads such as GLBenchmark TRex test. > > >> > > >> No piglit regression. > > >> > > >> v2 > > >> - no need to save the register before suspend as init_clock_gating can > > >> correctly program it after resume > > >> - split IVB change to another commit > > >> > > >> Signed-off-by: Chia-I Wu <olv@lunarg.com> > > > > > > What about byt? > > > -Daniel > > > > In the previous thread, Ville pointed out that the documentation > > doesn't say anything about BYT for this bit, so it's unknown whether > > it's supported, and Chia-I said > > > > > Though I will leave BDW/VLV out as I do not have the hardware. > > > > I do have BYT, so I'll check it out, but this patch can go in without > > it that information, since Chia-I took Ville's advice and split the > > patches into per-generation hunks. > > Make sense. Patches merged and I'll happily pull in the byt update if that > one checks out ok. and bdw also needs this (bspec says hsw+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 76126e0..c74bc28 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -934,6 +934,8 @@ #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) +#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d77cc81..c535e5c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4789,6 +4789,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:hsw */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:hsw */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));