diff mbox

[2/2] drm/i915: PSR HSW: update after enabling sprite.

Message ID 1391796588-2015-2-git-send-email-rodrigo.vivi@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi Feb. 7, 2014, 6:09 p.m. UTC
On the current structure HSW doesn't support PSR with sprites enabled
but sprites can be enabled after PSR was enabled what would cause
user to miss screen updates.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Daniel Vetter Feb. 7, 2014, 7 p.m. UTC | #1
On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote:
> On the current structure HSW doesn't support PSR with sprites enabled
> but sprites can be enabled after PSR was enabled what would cause
> user to miss screen updates.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Have you checked whether your current psr testcase hits this issue? If so
please add the Testcase: tag with the right subtest to this patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 336ae6c..3132686 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	I915_WRITE(SPRSURF(pipe),
>  		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
>  	POSTING_READ(SPRSURF(pipe));
> +
> +	intel_edp_psr_update(dev);
>  }
>  
>  static void
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjala Feb. 7, 2014, 7:17 p.m. UTC | #2
On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote:
> On the current structure HSW doesn't support PSR with sprites enabled
> but sprites can be enabled after PSR was enabled what would cause
> user to miss screen updates.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_sprite.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 336ae6c..3132686 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>  	I915_WRITE(SPRSURF(pipe),
>  		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
>  	POSTING_READ(SPRSURF(pipe));
> +
> +	intel_edp_psr_update(dev);

I was thinking this might be better placed in intel_update_plane()
since the fbc/ips stuff is there, but I can live with it being here too.

But should if have a HSW check on it? BDW doesn't have this restriction
anymore, right?

>  }
>  
>  static void
> -- 
> 1.7.11.7
Rodrigo Vivi Feb. 7, 2014, 7:24 p.m. UTC | #3
On Fri, Feb 7, 2014 at 5:17 PM, Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
> On Fri, Feb 07, 2014 at 04:09:48PM -0200, Rodrigo Vivi wrote:
>> On the current structure HSW doesn't support PSR with sprites enabled
>> but sprites can be enabled after PSR was enabled what would cause
>> user to miss screen updates.
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>> ---
>>  drivers/gpu/drm/i915/intel_sprite.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 336ae6c..3132686 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -318,6 +318,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>>       I915_WRITE(SPRSURF(pipe),
>>                  i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
>>       POSTING_READ(SPRSURF(pipe));
>> +
>> +     intel_edp_psr_update(dev);
>
> I was thinking this might be better placed in intel_update_plane()
> since the fbc/ips stuff is there, but I can live with it being here too.

I agree there is better.

>
> But should if have a HSW check on it? BDW doesn't have this restriction
> anymore, right?

yes, it should... you are right!
>
>>  }
>>
>>  static void
>> --
>> 1.7.11.7
>
> --
> Ville Syrjälä
> Intel OTC

I also agree with Daniel we need a test case for that...
so, will provide this and a new patch version later
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 336ae6c..3132686 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -318,6 +318,8 @@  ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(SPRSURF(pipe),
 		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 	POSTING_READ(SPRSURF(pipe));
+
+	intel_edp_psr_update(dev);
 }
 
 static void