[v2,10/23] ARM: MM: Add DT binding for Feroceon L2 cache

Message ID	1392459621-24003-11-git-send-email-andrew@lunn.ch (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Andrew Lunn <andrew@lunn.ch> To: Jason Cooper <jason@lakedaemon.net>, Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com>, Gregory Clement <gregory.clement@free-electrons.com> Subject: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache Date: Sat, 15 Feb 2014 11:20:08 +0100 Message-Id: <1392459621-24003-11-git-send-email-andrew@lunn.ch> In-Reply-To: <1392459621-24003-1-git-send-email-andrew@lunn.ch> References: <1392459621-24003-1-git-send-email-andrew@lunn.ch> Cc: Andrew Lunn <andrew@lunn.ch>, linux ARM <linux-arm-kernel@lists.infradead.org>, devicetree@vger.kernel.org Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org

Andrew Lunn Feb. 15, 2014, 10:20 a.m. UTC

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is and if write through should be made.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
cc: devicetree@vger.kernel.org
---
v2:
Change compatible strings to follow l2x0 convention
Only expect register for kirkwood-cache.
Default to write through if no DT node.
Rename writethrough to wt-override to follow l2cc binding.
Split kirkwood.dtsi change into a patch of its own.
---
 .../devicetree/bindings/arm/mrvl/feroceon.txt      | 17 +++++++
 arch/arm/include/asm/hardware/cache-feroceon-l2.h  |  2 +
 arch/arm/mach-kirkwood/board-dt.c                  | 15 +------
 arch/arm/mm/cache-feroceon-l2.c                    | 52 ++++++++++++++++++++++
 4 files changed, 72 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt

Arnd Bergmann Feb. 15, 2014, 1:23 p.m. UTC | #1

On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote:
> Instantiate the L2 cache from DT. Indicate in DT where the cache
> control register is and if write through should be made.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> cc: devicetree@vger.kernel.org
> 

I guess this answers part of my question for patch 5, but I also
wonder if the run-time setting is correct now with the hardcoded
#ifdef in arch/arm/mm/proc-feroceon.S checkign for the
Kconfig option. Presumably the code should match whatever is
set in the cache control register.

	Arnd

Andrew Lunn Feb. 15, 2014, 1:59 p.m. UTC | #2

On Sat, Feb 15, 2014 at 02:23:23PM +0100, Arnd Bergmann wrote:
> On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote:
> > Instantiate the L2 cache from DT. Indicate in DT where the cache
> > control register is and if write through should be made.
> > 
> > Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> > cc: devicetree@vger.kernel.org
> > 
> 
> I guess this answers part of my question for patch 5, but I also
> wonder if the run-time setting is correct now with the hardcoded
> #ifdef in arch/arm/mm/proc-feroceon.S checkign for the
> Kconfig option. Presumably the code should match whatever is
> set in the cache control register.

Humm, yes, good point.

None of the _defconfig's ever turn on
CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
not find any usage of it.

So i see two options:

1) Remove the wr-override from the DT binding and use
CACHE_FEROCEON_L2_WRITETHROUGH.

2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
the right thing at runtime.

I suspect i will go for 1), it is simpler.

  Thanks
	Andrew

Arnd Bergmann Feb. 15, 2014, 9:12 p.m. UTC | #3

On Saturday 15 February 2014, Andrew Lunn wrote:
> None of the _defconfig's ever turn on
> CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
> not find any usage of it.
> 
> So i see two options:
> 
> 1) Remove the wr-override from the DT binding and use
> CACHE_FEROCEON_L2_WRITETHROUGH.
> 
> 2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
> the right thing at runtime.
> 
> I suspect i will go for 1), it is simpler.

Yes, fair enough. I'd hope we could just kill the option altogether,
but it's probably hard to find anyone who would remember what it
was introduced for, unless Nico knows.

Git history points to 

commit 4360bb41920ffacd4a935fa692768129ee5bef4e
Author: Ronen Shitrit <rshitrit@marvell.com>
Date:   Tue Sep 23 15:28:10 2008 +0300

    [ARM] Kirkwood: add support for L2 cache WB/WT selection
    
    Feroceon L2 cache can work in eighther write through or write back mode
    on Kirkwood. Add the option to configure this mode according to Kconfig.
    
    Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
    Signed-off-by: Nicolas Pitre <nico@marvell.com>

	Arnd

Nicolas Pitre Feb. 15, 2014, 10:39 p.m. UTC | #4

On Sat, 15 Feb 2014, Arnd Bergmann wrote:

> On Saturday 15 February 2014, Andrew Lunn wrote:
> > None of the _defconfig's ever turn on
> > CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
> > not find any usage of it.
> > 
> > So i see two options:
> > 
> > 1) Remove the wr-override from the DT binding and use
> > CACHE_FEROCEON_L2_WRITETHROUGH.
> > 
> > 2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
> > the right thing at runtime.
> > 
> > I suspect i will go for 1), it is simpler.
> 
> Yes, fair enough. I'd hope we could just kill the option altogether,
> but it's probably hard to find anyone who would remember what it
> was introduced for, unless Nico knows.

There was a time when we didn't know what cache mode was the best 
performance wise.  The right answer is "it depends on the work load" of 
course.  Hence it was made optional for people to play with and choose 
for themselves.


Nicolas

Jason Cooper Feb. 17, 2014, 11:38 p.m. UTC | #5

On Sat, Feb 15, 2014 at 11:20:08AM +0100, Andrew Lunn wrote:
> Instantiate the L2 cache from DT. Indicate in DT where the cache
> control register is and if write through should be made.
> 
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
> cc: devicetree@vger.kernel.org
> ---
> v2:
> Change compatible strings to follow l2x0 convention
> Only expect register for kirkwood-cache.
> Default to write through if no DT node.
> Rename writethrough to wt-override to follow l2cc binding.
> Split kirkwood.dtsi change into a patch of its own.
> ---
>  .../devicetree/bindings/arm/mrvl/feroceon.txt      | 17 +++++++
>  arch/arm/include/asm/hardware/cache-feroceon-l2.h  |  2 +
>  arch/arm/mach-kirkwood/board-dt.c                  | 15 +------
>  arch/arm/mm/cache-feroceon-l2.c                    | 52 ++++++++++++++++++++++
>  4 files changed, 72 insertions(+), 14 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
> new file mode 100644
> index 000000000000..d6d7d6195ed1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
> @@ -0,0 +1,17 @@
> +* Marvell Feroceon Cache
> +
> +Required properties:
> +- compatible : Should be either "marvell,ferocean-cache" or
> +  	       "marvell,kirkwood-cache".
> +
> +Optional properties:
> +- wt-override: If present then L2 is forced to Write through mode
> +- reg        : Address of the L2 cache control register. Mandatory for
> +  	       "marvell,kirkwood-cache", not used by "marvell,ferocean-cache"

s/ferocean/feroceon/

If there's nothing else deserving a new series, I'll tweak this (and the
other spelling nits that matter) when I pull in the series.

thx,

Jason.

> +
> +
> +Example:
> +		l2: l2-cache@20128 {
> +			compatible = "marvell,kirkwood-cache";
> +			reg = <0x20128 0x4>;
> +		};
> diff --git a/arch/arm/include/asm/hardware/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
> index 8edd330aabf6..12e1588dc4f1 100644
> --- a/arch/arm/include/asm/hardware/cache-feroceon-l2.h
> +++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
> @@ -9,3 +9,5 @@
>   */
>  
>  extern void __init feroceon_l2_init(int l2_wt_override);
> +extern int __init feroceon_of_init(void);
> +
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 34c35510fd17..2ef59ee2182d 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -42,19 +42,6 @@ static void __init kirkwood_map_io(void)
>  	iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
>  }
>  
> -static void __init kirkwood_l2_init(void)
> -{
> -#ifdef CONFIG_CACHE_FEROCEON_L2
> -#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
> -	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
> -	feroceon_l2_init(1);
> -#else
> -	writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
> -	feroceon_l2_init(0);
> -#endif
> -#endif
> -}
> -
>  static struct resource kirkwood_cpufreq_resources[] = {
>  	[0] = {
>  		.start  = CPU_CONTROL_PHYS,
> @@ -211,7 +198,7 @@ static void __init kirkwood_dt_init(void)
>  
>  	BUG_ON(mvebu_mbus_dt_init());
>  
> -	kirkwood_l2_init();
> +	feroceon_of_init();
>  
>  	kirkwood_cpufreq_init();
>  	kirkwood_cpuidle_init();
> diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
> index 898362e7972b..17a1ecd7a40c 100644
> --- a/arch/arm/mm/cache-feroceon-l2.c
> +++ b/arch/arm/mm/cache-feroceon-l2.c
> @@ -13,11 +13,16 @@
>   */
>  
>  #include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
>  #include <linux/highmem.h>
> +#include <linux/io.h>
>  #include <asm/cacheflush.h>
>  #include <asm/cp15.h>
>  #include <asm/hardware/cache-feroceon-l2.h>
>  
> +#define L2_WRITETHROUGH_KIRKWOOD	BIT(4)
> +
>  /*
>   * Low-level cache maintenance operations.
>   *
> @@ -350,3 +355,50 @@ void __init feroceon_l2_init(int __l2_wt_override)
>  	printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
>  			 l2_wt_override ? ", in WT override mode" : "");
>  }
> +#ifdef CONFIG_OF
> +static const struct of_device_id feroceon_ids[] __initconst = {
> +	{ .compatible = "marvell,kirkwood-cache"},
> +	{ .compatible = "marvell,feroceon-cache"},
> +	{}
> +};
> +
> +int __init feroceon_of_init(void)
> +{
> +	struct device_node *node;
> +	void __iomem *base;
> +	bool l2_wt_override = false;
> +	struct resource res;
> +
> +	node = of_find_matching_node(NULL, feroceon_ids);
> +	if (!node) {
> +		/*
> +		 * If we don't know the write through state then
> +		 * assume it is write back, as that is the safest
> +		 * option.
> +		 */
> +		feroceon_l2_init(0);
> +		return 0;
> +	}
> +
> +	if (of_device_is_compatible(node, "marvell,kirkwood-cache")) {
> +		if (of_property_read_bool(node, "wt-override"))
> +			l2_wt_override = true;
> +
> +		if (of_address_to_resource(node, 0, &res))
> +			return -ENODEV;
> +
> +		base = ioremap(res.start, resource_size(&res));
> +		if (!base)
> +			return -ENOMEM;
> +
> +		if (l2_wt_override)
> +			writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
> +		else
> +			writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
> +	}
> +
> +	feroceon_l2_init(l2_wt_override);
> +
> +	return 0;
> +}
> +#endif
> -- 
> 1.8.5.3
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Andrew Lunn Feb. 18, 2014, 9:31 a.m. UTC | #6

> > +Required properties:
> > +- compatible : Should be either "marvell,ferocean-cache" or
> > +  	       "marvell,kirkwood-cache".
> > +
> > +Optional properties:
> > +- wt-override: If present then L2 is forced to Write through mode
> > +- reg        : Address of the L2 cache control register. Mandatory for
> > +  	       "marvell,kirkwood-cache", not used by "marvell,ferocean-cache"
> 
> s/ferocean/feroceon/

Arg. I thought i had fixed all of those.
 
> If there's nothing else deserving a new series, I'll tweak this (and the
> other spelling nits that matter) when I pull in the series.

This patch needs a major bit of re-working. There will definitely be a
new series.

    Andrew

[v2,10/23] ARM: MM: Add DT binding for Feroceon L2 cache

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