diff mbox

[v2,2/7] mmc: mmci: clarify DDR timing mode between SD-UHS and eMMC

Message ID 006101cf2a57$77859c00$6690d400$%jun@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Seungwon Jeon Feb. 15, 2014, 2:08 p.m. UTC
Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS.

CC: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
---
 drivers/mmc/host/mmci.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

Comments

Ulf Hansson Feb. 17, 2014, 2:08 p.m. UTC | #1
On 15 February 2014 15:08, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS.
>
> CC: Russell King <linux@arm.linux.org.uk>
> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>

Acked-by: Ulf Hansson <ulf.hansson@linaro.org>

Do note, normally Russell takes patches for mmci.

In this case I think it's important that the complete set gets merged
together. Especially since patch 1, on it's own, actually breaks
support for MMC DDR mode for some host drivers.

Kind regards
Ulf Hansson

> ---
>  drivers/mmc/host/mmci.c |    6 ++++--
>  1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index b931226..421d1fe 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -299,7 +299,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
>         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
>                 clk |= MCI_ST_8BIT_BUS;
>
> -       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
> +       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
> +           host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
>                 clk |= MCI_ST_UX500_NEG_EDGE;
>
>         mmci_write_clkreg(host, clk);
> @@ -784,7 +785,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
>                         mmci_write_clkreg(host, clk);
>                 }
>
> -       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
> +       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
> +           host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
>                 datactrl |= MCI_ST_DPSM_DDRMODE;
>
>         /*
> --
> 1.7.0.4
>
>
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Seungwon Jeon Feb. 18, 2014, 1:34 p.m. UTC | #2
On Mon, February 17, 2014, Ulf Hansson wrote:
> On 15 February 2014 15:08, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> > Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS.
> >
> > CC: Russell King <linux@arm.linux.org.uk>
> > Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
> 
> Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
> 
> Do note, normally Russell takes patches for mmci.
> 
> In this case I think it's important that the complete set gets merged
> together. Especially since patch 1, on it's own, actually breaks
> support for MMC DDR mode for some host drivers.

Thank you for your ack.
I also hope that.

Thanks,
Seungwon Jeon
> 
> Kind regards
> Ulf Hansson
> 
> > ---
> >  drivers/mmc/host/mmci.c |    6 ++++--
> >  1 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> > index b931226..421d1fe 100644
> > --- a/drivers/mmc/host/mmci.c
> > +++ b/drivers/mmc/host/mmci.c
> > @@ -299,7 +299,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
> >         if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
> >                 clk |= MCI_ST_8BIT_BUS;
> >
> > -       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
> > +       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
> > +           host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
> >                 clk |= MCI_ST_UX500_NEG_EDGE;
> >
> >         mmci_write_clkreg(host, clk);
> > @@ -784,7 +785,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
> >                         mmci_write_clkreg(host, clk);
> >                 }
> >
> > -       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
> > +       if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
> > +           host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
> >                 datactrl |= MCI_ST_DPSM_DDRMODE;
> >
> >         /*
> > --
> > 1.7.0.4
> >
> >
> --
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diff mbox

Patch

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index b931226..421d1fe 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -299,7 +299,8 @@  static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
 		clk |= MCI_ST_8BIT_BUS;
 
-	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
+	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
+	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 		clk |= MCI_ST_UX500_NEG_EDGE;
 
 	mmci_write_clkreg(host, clk);
@@ -784,7 +785,8 @@  static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 			mmci_write_clkreg(host, clk);
 		}
 
-	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
+	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
+	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
 		datactrl |= MCI_ST_DPSM_DDRMODE;
 
 	/*