diff mbox

[2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport

Message ID 1392873774-22249-2-git-send-email-mohit.kumar@st.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Mohit KUMAR DCG Feb. 20, 2014, 5:22 a.m. UTC 
This patch correct iATU programming for cfg1, io and mem viewport.
Enable ATU only after configuring it.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

Comments

Mohit KUMAR DCG Feb. 20, 2014, 6:45 a.m. UTC | #1 
+cc stable@vger.kerne.org

> -----Original Message-----

> From: Mohit KUMAR DCG

> Sent: Thursday, February 20, 2014 10:53 AM

> To: jg1.han@samsung.com

> Cc: Mohit KUMAR DCG; Ajay KHANDELWAL; Bjorn Helgaas; spear-devel;

> linux-pci@vger.kernel.org

> Subject: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and

> mem viewport

> 

> This patch correct iATU programming for cfg1, io and mem viewport.

> Enable ATU only after configuring it.

> 

> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>

> Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>

> Cc: Jingoo Han <jg1.han@samsung.com>

> Cc: Bjorn Helgaas <bhelgass@google.com>

> Cc: spear-devel@list.st.com

> Cc: linux-pci@vger.kernel.org

> ---

>  drivers/pci/host/pcie-designware.c |    6 +++---

>  1 files changed, 3 insertions(+), 3 deletions(-)

> 

> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-

> designware.c

> index 391966f..46f4a19 100644

> --- a/drivers/pci/host/pcie-designware.c

> +++ b/drivers/pci/host/pcie-designware.c

> @@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct

> pcie_port *pp, u32 busdev)

>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND |

> PCIE_ATU_REGION_INDEX1,

>  			  PCIE_ATU_VIEWPORT);

>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);

> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);

>  	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32),

> PCIE_ATU_UPPER_BASE);

>  	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,

>  			  PCIE_ATU_LIMIT);

>  	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);

>  	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);

> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  }

> 

>  static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)

> @@ -537,7 +537,6 @@ static void

> dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)

>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND |

> PCIE_ATU_REGION_INDEX0,

>  			  PCIE_ATU_VIEWPORT);

>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);

> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);

>  	dw_pcie_writel_rc(pp, (pp->mem_base >> 32),

> PCIE_ATU_UPPER_BASE);

>  	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,

> @@ -545,6 +544,7 @@ static void

> dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)

>  	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr,

> PCIE_ATU_LOWER_TARGET);

>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),

>  			  PCIE_ATU_UPPER_TARGET);

> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  }

> 

>  static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) @@

> -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct

> pcie_port *pp)

>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND |

> PCIE_ATU_REGION_INDEX1,

>  			  PCIE_ATU_VIEWPORT);

>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);

> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);

>  	dw_pcie_writel_rc(pp, (pp->io_base >> 32),

> PCIE_ATU_UPPER_BASE);

>  	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, @@ -

> 561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct

> pcie_port *pp)

>  	dw_pcie_writel_rc(pp, pp->config.io_bus_addr,

> PCIE_ATU_LOWER_TARGET);

>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),

>  			  PCIE_ATU_UPPER_TARGET);

> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);

>  }

> 

>  static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,

> --

> 1.7.0.1
Kishon Vijay Abraham I Feb. 20, 2014, 11:38 a.m. UTC | #2 
Hi,

On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> This patch correct iATU programming for cfg1, io and mem viewport.
> Enable ATU only after configuring it.

Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
this is more of cleaning up the sequence?

Thanks
Kishon

> 
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Bjorn Helgaas <bhelgass@google.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  drivers/pci/host/pcie-designware.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 391966f..46f4a19 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
>  			  PCIE_ATU_LIMIT);
>  	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> @@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
> @@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
>  			  PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
> @@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
>  			  PCIE_ATU_VIEWPORT);
>  	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
> -	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
>  	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
>  	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
> @@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
>  	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
>  			  PCIE_ATU_UPPER_TARGET);
> +	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
>  }
>  
>  static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> 

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Mohit KUMAR DCG Feb. 20, 2014, 11:58 a.m. UTC | #3 
Hello Kishon,

> -----Original Message-----

> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]

> Sent: Thursday, February 20, 2014 5:08 PM

> To: Mohit KUMAR DCG; jg1.han@samsung.com

> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-

> pci@vger.kernel.org

> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io

> and mem viewport

> 

> Hi,

> 

> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:

> > This patch correct iATU programming for cfg1, io and mem viewport.

> > Enable ATU only after configuring it.

> 

> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or

> this is more of cleaning up the sequence?

> 

- This patch corrects ATU programming sequence. I am not aware of any such issue with
current driver. Pls specify  which bridge do you use in your setup and what is the problem?

Regards
Mohit
Kishon Vijay Abraham I Feb. 20, 2014, 12:13 p.m. UTC | #4 
Hi Mohit,

On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> Hello Kishon,
> 
>> -----Original Message-----
>> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
>> Sent: Thursday, February 20, 2014 5:08 PM
>> To: Mohit KUMAR DCG; jg1.han@samsung.com
>> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
>> pci@vger.kernel.org
>> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
>> and mem viewport
>>
>> Hi,
>>
>> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
>>> This patch correct iATU programming for cfg1, io and mem viewport.
>>> Enable ATU only after configuring it.
>>
>> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
>> this is more of cleaning up the sequence?
>>
> - This patch corrects ATU programming sequence. I am not aware of any such issue with
> current driver. Pls specify  which bridge do you use in your setup and what is the problem?

I tried with card [1], it had a PLX bridge chip. It couldn't read the
configuration space of the device connected to the PCIe-PCI bridge.

Thanks
Kishon

[1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.

> 
> Regards
> Mohit
> 

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Mohit KUMAR DCG Feb. 20, 2014, 1:33 p.m. UTC | #5 
Hello Kishon,

> -----Original Message-----

> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]

> Sent: Thursday, February 20, 2014 5:43 PM

> To: Mohit KUMAR DCG; jg1.han@samsung.com

> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-

> pci@vger.kernel.org

> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io

> and mem viewport

> 

> Hi Mohit,

> 

> On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:

> > Hello Kishon,

> >

> >> -----Original Message-----

> >> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]

> >> Sent: Thursday, February 20, 2014 5:08 PM

> >> To: Mohit KUMAR DCG; jg1.han@samsung.com

> >> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-

> >> pci@vger.kernel.org

> >> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for

> >> cfg1, io and mem viewport

> >>

> >> Hi,

> >>

> >> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:

> >>> This patch correct iATU programming for cfg1, io and mem viewport.

> >>> Enable ATU only after configuring it.

> >>

> >> Does this patch actually fixes device enumeration behind a PCIe-pci

> >> bridge or this is more of cleaning up the sequence?

> >>

> > - This patch corrects ATU programming sequence. I am not aware of any

> > such issue with current driver. Pls specify  which bridge do you use in your

> setup and what is the problem?

> 

> I tried with card [1], it had a PLX bridge chip. It couldn't read the configuration

> space of the device connected to the PCIe-PCI bridge.

> 

- I don’t have the mentioned card with me, but we are successfully using Lecroy PTC switch
 and SIL3124-2CB364 PCI-X compatible RAID card.

May be Jingoo or others can also comment if they are using PCI bridge card.

Thanks
Mohit
Pratyush ANAND Feb. 21, 2014, 3:54 a.m. UTC | #6 
On Thu, Feb 20, 2014 at 08:13:08PM +0800, Kishon Vijay Abraham I wrote:
> Hi Mohit,
> 
> On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> > Hello Kishon,
> > 
> >> -----Original Message-----
> >> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> >> Sent: Thursday, February 20, 2014 5:08 PM
> >> To: Mohit KUMAR DCG; jg1.han@samsung.com
> >> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
> >> pci@vger.kernel.org
> >> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
> >> and mem viewport
> >>
> >> Hi,
> >>
> >> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> >>> This patch correct iATU programming for cfg1, io and mem viewport.
> >>> Enable ATU only after configuring it.
> >>
> >> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
> >> this is more of cleaning up the sequence?
> >>
> > - This patch corrects ATU programming sequence. I am not aware of any such issue with
> > current driver. Pls specify  which bridge do you use in your setup and what is the problem?
> 
> I tried with card [1], it had a PLX bridge chip. It couldn't read the
> configuration space of the device connected to the PCIe-PCI bridge.

So do you see abort while reading config space of device connected to
the PCIe-PCI bridge?

Do you see "received master abort" bit set in your RC's cfg register
after you try to read?

Regards
Pratyush

> 
> Thanks
> Kishon
> 
> [1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.
> 
> > 
> > Regards
> > Mohit
> > 
> 
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diff mbox

Patch

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 391966f..46f4a19 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -522,13 +522,13 @@  static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
 			  PCIE_ATU_LIMIT);
 	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -537,7 +537,6 @@  static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -545,6 +544,7 @@  static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -553,7 +553,6 @@  static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -561,6 +560,7 @@  static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,