| Message ID | 1393541406-13472-1-git-send-email-zhenyuw@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 28, 2014 at 06:50:06AM +0800, Zhenyu Wang wrote: > >From spec the drain latency precision multipler is either 32 or 64 for VLV. > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++--------- > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ > 2 files changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2f564ce..cb6509c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3381,19 +3381,19 @@ > > /* drain latency register values*/ > #define DRAIN_LATENCY_PRECISION_32 32 > -#define DRAIN_LATENCY_PRECISION_16 16 > +#define DRAIN_LATENCY_PRECISION_64 64 > #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) > -#define DDL_CURSORA_PRECISION_32 (1<<31) > -#define DDL_CURSORA_PRECISION_16 (0<<31) > +#define DDL_CURSORA_PRECISION_64 (1<<31) > +#define DDL_CURSORA_PRECISION_32 (0<<31) > #define DDL_CURSORA_SHIFT 24 > -#define DDL_PLANEA_PRECISION_32 (1<<7) > -#define DDL_PLANEA_PRECISION_16 (0<<7) > +#define DDL_PLANEA_PRECISION_64 (1<<7) > +#define DDL_PLANEA_PRECISION_32 (0<<7) > #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) > -#define DDL_CURSORB_PRECISION_32 (1<<31) > -#define DDL_CURSORB_PRECISION_16 (0<<31) > +#define DDL_CURSORB_PRECISION_64 (1<<31) > +#define DDL_CURSORB_PRECISION_32 (0<<31) > #define DDL_CURSORB_SHIFT 24 > -#define DDL_PLANEB_PRECISION_32 (1<<7) > -#define DDL_PLANEB_PRECISION_16 (0<<7) > +#define DDL_PLANEB_PRECISION_64 (1<<7) > +#define DDL_PLANEB_PRECISION_32 (0<<7) > > /* FIFO watermark sizes etc */ > #define G4X_FIFO_LINE_SIZE 64 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a6b877a..b17b396 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1248,13 +1248,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, > > entries = (clock / 1000) * pixel_size; > *plane_prec_mult = (entries > 256) ? The threshold should also be reduced to 128 entries. > - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; > + DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * > pixel_size); ^^^^^^^^^^^^^^^^^ Maybe replace the divisor here w/ just 'entrie' since it's same thing. Makes it a bit easier to see the relationship between this and the way the precision is selected. > > entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ > *cursor_prec_mult = (entries > 256) ? ditto about threshold > - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; > + DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); ^^^^^^^^^^^^^^^^^^^^ Again could just say 'entries' > > return true; > @@ -1280,9 +1280,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) > if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, > &cursor_prec_mult, &cursora_dl)) { > cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? > - DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; > + DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64; > planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? > - DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; > + DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64; > > I915_WRITE(VLV_DDL1, cursora_prec | > (cursora_dl << DDL_CURSORA_SHIFT) | > @@ -1293,9 +1293,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) > if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, > &cursor_prec_mult, &cursorb_dl)) { > cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? > - DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; > + DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64; > planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? > - DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; > + DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64; > > I915_WRITE(VLV_DDL2, cursorb_prec | > (cursorb_dl << DDL_CURSORB_SHIFT) | > -- > 1.9.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 2014.03.05 18:51:48 +0200, Ville Syrjälä wrote: > > entries = (clock / 1000) * pixel_size; > > *plane_prec_mult = (entries > 256) ? > > The threshold should also be reduced to 128 entries. > hmm, I'll double check if this is really required or not. > > - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; > > + DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; > > *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * > > pixel_size); > ^^^^^^^^^^^^^^^^^ > Maybe replace the divisor here w/ just 'entrie' since it's same thing. > Makes it a bit easier to see the relationship between this and the way > the precision is selected. > yeah, but that might be another seperate patch besides the precision multipler this one trys to fix. Thanks for review this.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f564ce..cb6509c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3381,19 +3381,19 @@ /* drain latency register values*/ #define DRAIN_LATENCY_PRECISION_32 32 -#define DRAIN_LATENCY_PRECISION_16 16 +#define DRAIN_LATENCY_PRECISION_64 64 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) -#define DDL_CURSORA_PRECISION_32 (1<<31) -#define DDL_CURSORA_PRECISION_16 (0<<31) +#define DDL_CURSORA_PRECISION_64 (1<<31) +#define DDL_CURSORA_PRECISION_32 (0<<31) #define DDL_CURSORA_SHIFT 24 -#define DDL_PLANEA_PRECISION_32 (1<<7) -#define DDL_PLANEA_PRECISION_16 (0<<7) +#define DDL_PLANEA_PRECISION_64 (1<<7) +#define DDL_PLANEA_PRECISION_32 (0<<7) #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) -#define DDL_CURSORB_PRECISION_32 (1<<31) -#define DDL_CURSORB_PRECISION_16 (0<<31) +#define DDL_CURSORB_PRECISION_64 (1<<31) +#define DDL_CURSORB_PRECISION_32 (0<<31) #define DDL_CURSORB_SHIFT 24 -#define DDL_PLANEB_PRECISION_32 (1<<7) -#define DDL_PLANEB_PRECISION_16 (0<<7) +#define DDL_PLANEB_PRECISION_64 (1<<7) +#define DDL_PLANEB_PRECISION_32 (0<<7) /* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a6b877a..b17b396 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1248,13 +1248,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, entries = (clock / 1000) * pixel_size; *plane_prec_mult = (entries > 256) ? - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; + DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * pixel_size); entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ *cursor_prec_mult = (entries > 256) ? - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; + DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); return true; @@ -1280,9 +1280,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, &cursor_prec_mult, &cursora_dl)) { cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? - DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; + DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64; planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? - DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; + DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64; I915_WRITE(VLV_DDL1, cursora_prec | (cursora_dl << DDL_CURSORA_SHIFT) | @@ -1293,9 +1293,9 @@ static void vlv_update_drain_latency(struct drm_device *dev) if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, &cursor_prec_mult, &cursorb_dl)) { cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? - DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; + DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64; planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? - DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; + DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64; I915_WRITE(VLV_DDL2, cursorb_prec | (cursorb_dl << DDL_CURSORB_SHIFT) |
From spec the drain latency precision multipler is either 32 or 64 for VLV. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++--------- drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ 2 files changed, 15 insertions(+), 15 deletions(-)