| Message ID | 1394233836-3827-9-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Mar 07, 2014 at 08:10:24PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Instead of trying to clear it again. It should already be masked and > disabled and zeroed at preinstall/uninstall. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 32 +++++++++++++++----------------- > 1 file changed, 15 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 6d4daf2..4d0a8b1 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -103,12 +103,24 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ > I915_WRITE(type##IIR, 0xffffffff); \ > } while (0) > > +/* > + * We should clear IMR at preinstall/uninstall, and just check at postinstall. > + */ > +#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ > + u32 val = I915_READ(reg); \ > + if (val) \ > + DRM_ERROR("Interrupt register 0x%x is not zero: 0x%08x\n", \ > + (reg), val); \ > +} while (0) > + > #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ > + GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ > I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ > I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ > } while (0) > > #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ > + GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ > I915_WRITE(type##IMR, (imr_val)); \ > I915_WRITE(type##IER, (ier_val)); \ > } while (0) Okay, this is replacing a POSTED_WRITE, with a (slower) POSTING_READ which gives an error that we can do nothing about other than clear it anyway. I'd be in favor of dropping this patch. > @@ -2940,7 +2952,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) > I915_WRITE(SERR_INT, I915_READ(SERR_INT)); > } > > - I915_WRITE(SDEIIR, I915_READ(SDEIIR)); > + GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); > I915_WRITE(SDEIMR, ~mask); > } > > @@ -2966,7 +2978,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; > } > > - I915_WRITE(GTIIR, I915_READ(GTIIR)); > GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); > > if (INTEL_INFO(dev)->gen >= 6) { > @@ -2976,7 +2987,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > pm_irqs |= PM_VEBOX_USER_INTERRUPT; > > dev_priv->pm_irq_mask = 0xffffffff; > - I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); > GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); > } > POSTING_READ(GTIER); > @@ -3010,8 +3020,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > > dev_priv->irq_mask = ~display_mask; > > - /* should always can generate irq */ > - I915_WRITE(DEIIR, I915_READ(DEIIR)); > GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); > > gen5_gt_irq_postinstall(dev); > @@ -3172,13 +3180,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) > GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT > }; > > - for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { > - u32 tmp = I915_READ(GEN8_GT_IIR(i)); > - if (tmp) > - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", > - i, tmp); > + for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) > GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); > - } > POSTING_READ(GEN8_GT_IER(0)); > } > > @@ -3195,14 +3198,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; > dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; > > - for_each_pipe(pipe) { > - u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); > - if (tmp) > - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", > - pipe, tmp); > + for_each_pipe(pipe) > GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], > de_pipe_enables); > - } > POSTING_READ(GEN8_DE_PIPE_ISR(0)); > > GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); > -- > 1.8.5.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Mar 18, 2014 at 11:20:09AM -0700, Ben Widawsky wrote: > On Fri, Mar 07, 2014 at 08:10:24PM -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > Instead of trying to clear it again. It should already be masked and > > disabled and zeroed at preinstall/uninstall. > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 32 +++++++++++++++----------------- > > 1 file changed, 15 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 6d4daf2..4d0a8b1 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -103,12 +103,24 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ > > I915_WRITE(type##IIR, 0xffffffff); \ > > } while (0) > > > > +/* > > + * We should clear IMR at preinstall/uninstall, and just check at postinstall. > > + */ > > +#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ > > + u32 val = I915_READ(reg); \ > > + if (val) \ > > + DRM_ERROR("Interrupt register 0x%x is not zero: 0x%08x\n", \ > > + (reg), val); \ > > +} while (0) > > + > > #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ > > + GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ > > I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ > > I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ > > } while (0) > > > > #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ > > + GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ > > I915_WRITE(type##IMR, (imr_val)); \ > > I915_WRITE(type##IER, (ier_val)); \ > > } while (0) > > Okay, this is replacing a POSTED_WRITE, with a (slower) POSTING_READ > which gives an error that we can do nothing about other than clear it > anyway. > > I'd be in favor of dropping this patch. The point of the assert is to make sure that the new IIR clearing logic with blocking everything+clearing in the preinstall hook actually does what it's supposed to do. Since the point of this exercise is to reuse this code for runtime suspend/resume where races are much easier to hit I think this is a good self-check of the code. -Daniel > > > @@ -2940,7 +2952,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) > > I915_WRITE(SERR_INT, I915_READ(SERR_INT)); > > } > > > > - I915_WRITE(SDEIIR, I915_READ(SDEIIR)); > > + GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); > > I915_WRITE(SDEIMR, ~mask); > > } > > > > @@ -2966,7 +2978,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; > > } > > > > - I915_WRITE(GTIIR, I915_READ(GTIIR)); > > GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); > > > > if (INTEL_INFO(dev)->gen >= 6) { > > @@ -2976,7 +2987,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > > pm_irqs |= PM_VEBOX_USER_INTERRUPT; > > > > dev_priv->pm_irq_mask = 0xffffffff; > > - I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); > > GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); > > } > > POSTING_READ(GTIER); > > @@ -3010,8 +3020,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > > > > dev_priv->irq_mask = ~display_mask; > > > > - /* should always can generate irq */ > > - I915_WRITE(DEIIR, I915_READ(DEIIR)); > > GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); > > > > gen5_gt_irq_postinstall(dev); > > @@ -3172,13 +3180,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) > > GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT > > }; > > > > - for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { > > - u32 tmp = I915_READ(GEN8_GT_IIR(i)); > > - if (tmp) > > - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", > > - i, tmp); > > + for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) > > GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); > > - } > > POSTING_READ(GEN8_GT_IER(0)); > > } > > > > @@ -3195,14 +3198,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; > > dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; > > > > - for_each_pipe(pipe) { > > - u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); > > - if (tmp) > > - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", > > - pipe, tmp); > > + for_each_pipe(pipe) > > GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], > > de_pipe_enables); > > - } > > POSTING_READ(GEN8_DE_PIPE_ISR(0)); > > > > GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A); > > -- > > 1.8.5.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ben Widawsky, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Mar 19, 2014 at 09:28:32AM +0100, Daniel Vetter wrote: > On Tue, Mar 18, 2014 at 11:20:09AM -0700, Ben Widawsky wrote: > > On Fri, Mar 07, 2014 at 08:10:24PM -0300, Paulo Zanoni wrote: > > > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > > > Instead of trying to clear it again. It should already be masked and > > > disabled and zeroed at preinstall/uninstall. > > > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_irq.c | 32 +++++++++++++++----------------- > > > 1 file changed, 15 insertions(+), 17 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > > index 6d4daf2..4d0a8b1 100644 > > > --- a/drivers/gpu/drm/i915/i915_irq.c > > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > > @@ -103,12 +103,24 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ > > > I915_WRITE(type##IIR, 0xffffffff); \ > > > } while (0) > > > > > > +/* > > > + * We should clear IMR at preinstall/uninstall, and just check at postinstall. > > > + */ > > > +#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ > > > + u32 val = I915_READ(reg); \ > > > + if (val) \ > > > + DRM_ERROR("Interrupt register 0x%x is not zero: 0x%08x\n", \ > > > + (reg), val); \ > > > +} while (0) > > > + > > > #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ > > > + GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ > > > I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ > > > I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ > > > } while (0) > > > > > > #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ > > > + GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ > > > I915_WRITE(type##IMR, (imr_val)); \ > > > I915_WRITE(type##IER, (ier_val)); \ > > > } while (0) > > > > Okay, this is replacing a POSTED_WRITE, with a (slower) POSTING_READ > > which gives an error that we can do nothing about other than clear it > > anyway. > > > > I'd be in favor of dropping this patch. > > The point of the assert is to make sure that the new IIR clearing logic > with blocking everything+clearing in the preinstall hook actually does > what it's supposed to do. > > Since the point of this exercise is to reuse this code for runtime > suspend/resume where races are much easier to hit I think this is a good > self-check of the code. > -Daniel > Okay, I am feeling somewhat pressured to stick a reviewed-by on this since Daniel likes it. Change the macro to WARN instead of DRM_ERROR, and, clear the IIR if it's non-zero. With that change, it's: Reviewed-by-with-reservations: Ben Widawsky <ben@bwidawsk.net>
2014-03-19 14:50 GMT-03:00 Ben Widawsky <ben@bwidawsk.net>: > On Wed, Mar 19, 2014 at 09:28:32AM +0100, Daniel Vetter wrote: >> On Tue, Mar 18, 2014 at 11:20:09AM -0700, Ben Widawsky wrote: >> > On Fri, Mar 07, 2014 at 08:10:24PM -0300, Paulo Zanoni wrote: >> > > From: Paulo Zanoni <paulo.r.zanoni@intel.com> >> > > >> > > Instead of trying to clear it again. It should already be masked and >> > > disabled and zeroed at preinstall/uninstall. >> > > >> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >> > > --- >> > > drivers/gpu/drm/i915/i915_irq.c | 32 +++++++++++++++----------------- >> > > 1 file changed, 15 insertions(+), 17 deletions(-) >> > > >> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> > > index 6d4daf2..4d0a8b1 100644 >> > > --- a/drivers/gpu/drm/i915/i915_irq.c >> > > +++ b/drivers/gpu/drm/i915/i915_irq.c >> > > @@ -103,12 +103,24 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ >> > > I915_WRITE(type##IIR, 0xffffffff); \ >> > > } while (0) >> > > >> > > +/* >> > > + * We should clear IMR at preinstall/uninstall, and just check at postinstall. >> > > + */ >> > > +#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ >> > > + u32 val = I915_READ(reg); \ >> > > + if (val) \ >> > > + DRM_ERROR("Interrupt register 0x%x is not zero: 0x%08x\n", \ >> > > + (reg), val); \ >> > > +} while (0) >> > > + >> > > #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ >> > > + GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ >> > > I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ >> > > I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ >> > > } while (0) >> > > >> > > #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ >> > > + GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ >> > > I915_WRITE(type##IMR, (imr_val)); \ >> > > I915_WRITE(type##IER, (ier_val)); \ >> > > } while (0) >> > >> > Okay, this is replacing a POSTED_WRITE, with a (slower) POSTING_READ >> > which gives an error that we can do nothing about other than clear it >> > anyway. >> > >> > I'd be in favor of dropping this patch. >> >> The point of the assert is to make sure that the new IIR clearing logic >> with blocking everything+clearing in the preinstall hook actually does >> what it's supposed to do. >> >> Since the point of this exercise is to reuse this code for runtime >> suspend/resume where races are much easier to hit I think this is a good >> self-check of the code. Just an additional comment: the current code just writes to IIR once in case it's not zero, and this is not a guarantee that it will be cleared. So if we decided to drop this patch, I would suggest to fix the IIR-clearing code. >> -Daniel >> > > Okay, I am feeling somewhat pressured to stick a reviewed-by on this > since Daniel likes it. > > Change the macro to WARN instead of DRM_ERROR, and, clear the IIR if > it's non-zero. With that change, it's: > Reviewed-by-with-reservations: Ben Widawsky <ben@bwidawsk.net> > > -- > Ben Widawsky, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6d4daf2..4d0a8b1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -103,12 +103,24 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ I915_WRITE(type##IIR, 0xffffffff); \ } while (0) +/* + * We should clear IMR at preinstall/uninstall, and just check at postinstall. + */ +#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ + u32 val = I915_READ(reg); \ + if (val) \ + DRM_ERROR("Interrupt register 0x%x is not zero: 0x%08x\n", \ + (reg), val); \ +} while (0) + #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ + GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ } while (0) #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ + GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ I915_WRITE(type##IMR, (imr_val)); \ I915_WRITE(type##IER, (ier_val)); \ } while (0) @@ -2940,7 +2952,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) I915_WRITE(SERR_INT, I915_READ(SERR_INT)); } - I915_WRITE(SDEIIR, I915_READ(SDEIIR)); + GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); I915_WRITE(SDEIMR, ~mask); } @@ -2966,7 +2978,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; } - I915_WRITE(GTIIR, I915_READ(GTIIR)); GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); if (INTEL_INFO(dev)->gen >= 6) { @@ -2976,7 +2987,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) pm_irqs |= PM_VEBOX_USER_INTERRUPT; dev_priv->pm_irq_mask = 0xffffffff; - I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); } POSTING_READ(GTIER); @@ -3010,8 +3020,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev) dev_priv->irq_mask = ~display_mask; - /* should always can generate irq */ - I915_WRITE(DEIIR, I915_READ(DEIIR)); GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -3172,13 +3180,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT }; - for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { - u32 tmp = I915_READ(GEN8_GT_IIR(i)); - if (tmp) - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", - i, tmp); + for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]); - } POSTING_READ(GEN8_GT_IER(0)); } @@ -3195,14 +3198,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; - for_each_pipe(pipe) { - u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); - if (tmp) - DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", - pipe, tmp); + for_each_pipe(pipe) GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], de_pipe_enables); - } POSTING_READ(GEN8_DE_PIPE_ISR(0)); GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);