diff mbox

drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIK

Message ID 1395501643-17788-1-git-send-email-maraeo@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Marek Olšák March 22, 2014, 3:20 p.m. UTC 
From: Marek Olšák <marek.olsak@amd.com>

This fixes fast color clear with 1D-tiled single-sample surfaces
and Hyper-Z corruption with 1D-tiled depth surfaces.

Even though it seems it is not needed for 1D tiling, CMASK and HTILE are
always 2D-tiled, thus the hw needs to know the actual pipe configuration
for CMASK and HTILE addressing no matter what the tiling mode of the surface
is.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
 drivers/gpu/drm/radeon/cik.c        | 27 ++++++++++++++++++++++++---
 drivers/gpu/drm/radeon/radeon_drv.c |  3 ++-
 2 files changed, 26 insertions(+), 4 deletions(-)

Comments

Alex Deucher March 22, 2014, 5:25 p.m. UTC | #1 
On Sat, Mar 22, 2014 at 11:20 AM, Marek Olšák <maraeo@gmail.com> wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> This fixes fast color clear with 1D-tiled single-sample surfaces
> and Hyper-Z corruption with 1D-tiled depth surfaces.
>
> Even though it seems it is not needed for 1D tiling, CMASK and HTILE are
> always 2D-tiled, thus the hw needs to know the actual pipe configuration
> for CMASK and HTILE addressing no matter what the tiling mode of the surface
> is.
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>

Applied to my -fixes tree.  Depending on when 3.14 goes final, this
may slip to 3.15.

Alex

> ---
>  drivers/gpu/drm/radeon/cik.c        | 27 ++++++++++++++++++++++++---
>  drivers/gpu/drm/radeon/radeon_drv.c |  3 ++-
>  2 files changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index bbb1784..9bfd3d3 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -2028,6 +2028,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 5:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
>                                 break;
>                         case 6:
> @@ -2048,6 +2049,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 9:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
>                                 break;
>                         case 10:
> @@ -2070,6 +2072,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 13:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
>                                 break;
>                         case 14:
> @@ -2092,6 +2095,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 27:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
>                                 break;
>                         case 28:
> @@ -2246,6 +2250,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 5:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
>                                 break;
>                         case 6:
> @@ -2266,6 +2271,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 9:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
>                                 break;
>                         case 10:
> @@ -2288,6 +2294,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 13:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
>                                 break;
>                         case 14:
> @@ -2310,6 +2317,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 27:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
>                                 break;
>                         case 28:
> @@ -2466,6 +2474,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 5:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
>                                         break;
>                                 case 6:
> @@ -2486,6 +2495,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 9:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
>                                         break;
>                                 case 10:
> @@ -2508,6 +2518,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 13:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
>                                         break;
>                                 case 14:
> @@ -2530,6 +2541,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 27:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
>                                         break;
>                                 case 28:
> @@ -2592,6 +2604,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 5:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
>                                         break;
>                                 case 6:
> @@ -2612,6 +2625,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 9:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
>                                         break;
>                                 case 10:
> @@ -2634,6 +2648,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 13:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
>                                         break;
>                                 case 14:
> @@ -2656,6 +2671,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 27:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
>                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
>                                         break;
>                                 case 28:
> @@ -2812,6 +2828,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 5:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
>                                 break;
>                         case 6:
> @@ -2827,11 +2844,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                                  TILE_SPLIT(split_equal_to_row_size));
>                                 break;
>                         case 8:
> -                               gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
> +                               gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> +                                               PIPE_CONFIG(ADDR_SURF_P2);
>                                 break;
>                         case 9:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2));
>                                 break;
>                         case 10:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2853,6 +2872,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 13:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2) |
>                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
>                                 break;
>                         case 14:
> @@ -2875,7 +2895,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 27:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2));
>                                 break;
>                         case 28:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
> index 84a1bbb7..b2694c1 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -79,9 +79,10 @@
>   *   2.35.0 - Add CIK macrotile mode array query
>   *   2.36.0 - Fix CIK DCE tiling setup
>   *   2.37.0 - allow GS ring setup on r6xx/r7xx
> + *   2.38.0 - CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
>   */
>  #define KMS_DRIVER_MAJOR       2
> -#define KMS_DRIVER_MINOR       37
> +#define KMS_DRIVER_MINOR       38
>  #define KMS_DRIVER_PATCHLEVEL  0
>  int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
>  int radeon_driver_unload_kms(struct drm_device *dev);
> --
> 1.8.3.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index bbb1784..9bfd3d3 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2028,6 +2028,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 5:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 				break;
 			case 6:
@@ -2048,6 +2049,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 9:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 				break;
 			case 10:
@@ -2070,6 +2072,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 13:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 				break;
 			case 14:
@@ -2092,6 +2095,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 27:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 				break;
 			case 28:
@@ -2246,6 +2250,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 5:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 				break;
 			case 6:
@@ -2266,6 +2271,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 9:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 				break;
 			case 10:
@@ -2288,6 +2294,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 13:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 				break;
 			case 14:
@@ -2310,6 +2317,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 27:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 				break;
 			case 28:
@@ -2466,6 +2474,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 5:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 					break;
 				case 6:
@@ -2486,6 +2495,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 9:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 					break;
 				case 10:
@@ -2508,6 +2518,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 13:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 					break;
 				case 14:
@@ -2530,6 +2541,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 27:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 					break;
 				case 28:
@@ -2592,6 +2604,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 5:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 					break;
 				case 6:
@@ -2612,6 +2625,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 9:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 					break;
 				case 10:
@@ -2634,6 +2648,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 13:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 					break;
 				case 14:
@@ -2656,6 +2671,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 27:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 					break;
 				case 28:
@@ -2812,6 +2828,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 5:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P2) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 				break;
 			case 6:
@@ -2827,11 +2844,13 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 						 TILE_SPLIT(split_equal_to_row_size));
 				break;
 			case 8:
-				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
+				gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+						PIPE_CONFIG(ADDR_SURF_P2);
 				break;
 			case 9:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P2));
 				break;
 			case 10:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2853,6 +2872,7 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 13:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 PIPE_CONFIG(ADDR_SURF_P2) |
 						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 				break;
 			case 14:
@@ -2875,7 +2895,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 27:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P2));
 				break;
 			case 28:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 84a1bbb7..b2694c1 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -79,9 +79,10 @@ 
  *   2.35.0 - Add CIK macrotile mode array query
  *   2.36.0 - Fix CIK DCE tiling setup
  *   2.37.0 - allow GS ring setup on r6xx/r7xx
+ *   2.38.0 - CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  */
 #define KMS_DRIVER_MAJOR	2
-#define KMS_DRIVER_MINOR	37
+#define KMS_DRIVER_MINOR	38
 #define KMS_DRIVER_PATCHLEVEL	0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);