| Message ID | 1395736265-20419-1-git-send-email-sourab.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Mar 25, 2014 at 02:01:05PM +0530, sourab.gupta@intel.com wrote: > From: Akash Goel <akash.goel@intel.com> > > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. > This workaround has to be applied before doing TLB Invalidation. > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > Store data commands. > Without this, hardware cannot guarantee the command after the PIPE_CONTROL > with TLB inv will not use the old TLB values. > > v2: Modified the WA comment (Ville) > > v3: Added the vlv identifier with WA name (Damien) > > v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, > sending 6 dwords instead of 8) (Chris) > > v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being > called from gen6, gen7 flush functions. (Ville) > > @@ -1733,6 +1771,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, > uint32_t cmd; > int ret; > > + /* Apply WaTlbInvalidateStoreDataBefore workaround */ > + if (invalidate) { > + ret = gen6_tlb_invalidate_wa(ring); > + if (ret) > + return ret; > + } BSD uses MI_FLUSH_DW. Does this w/a still apply? Do we need it for BLT as well? VEBOX? -Chris
On Tue, 2014-03-25 at 09:15 +0000, Chris Wilson wrote: > On Tue, Mar 25, 2014 at 02:01:05PM +0530, sourab.gupta@intel.com wrote: > > From: Akash Goel <akash.goel@intel.com> > > > > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. > > This workaround has to be applied before doing TLB Invalidation. > > In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI > > Store data commands. > > Without this, hardware cannot guarantee the command after the PIPE_CONTROL > > with TLB inv will not use the old TLB values. > > > > v2: Modified the WA comment (Ville) > > > > v3: Added the vlv identifier with WA name (Damien) > > > > v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, > > sending 6 dwords instead of 8) (Chris) > > > > v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being > > called from gen6, gen7 flush functions. (Ville) > > > > @@ -1733,6 +1771,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, > > uint32_t cmd; > > int ret; > > > > + /* Apply WaTlbInvalidateStoreDataBefore workaround */ > > + if (invalidate) { > > + ret = gen6_tlb_invalidate_wa(ring); > > + if (ret) > > + return ret; > > + } > > BSD uses MI_FLUSH_DW. Does this w/a still apply? Do we need it for BLT > as well? VEBOX? > -Chris > This should be applicable only to the render ring funcs, not the bsd, blt, vebox ones, as you called out. PIPE_CONTROL is used only in render ring, others use MI_FLUSH. My bad for missing this out. Thanks, Sourab
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 87d1a2d..ef4ca3dd 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -208,6 +208,30 @@ intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) } static int +gen6_tlb_invalidate_wa(struct intel_ring_buffer *ring) +{ + /* + * WaTlbInvalidateStoreDataBefore:gen6,gen7 + * This workaround has to be applied before doing TLB invalidation. + * Before pipecontrol with TLB invalidate set, need 2 store + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) + * Without this, hardware cannot guarantee the command after the + * PIPE_CONTROL with TLB inv will not use the old TLB values. + */ + int i, ret; + ret = intel_ring_begin(ring, 3 * 2); + if (ret) + return ret; + for (i = 0; i < 2; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); + return 0; +} + +static int gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) { @@ -215,6 +239,13 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* Force SNB workarounds for PIPE_CONTROL flushes */ ret = intel_emit_post_sync_nonzero_flush(ring); if (ret) @@ -309,6 +340,13 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed. @@ -1733,6 +1771,13 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, uint32_t cmd; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + ret = intel_ring_begin(ring, 4); if (ret) return ret; @@ -1837,6 +1882,13 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, uint32_t cmd; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + ret = intel_ring_begin(ring, 4); if (ret) return ret;