| Message ID | 1396611878-23268-1-git-send-email-sourab.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta@intel.com wrote: > From: Akash Goel <akash.goel@intel.com> > > On Gen4+ platforms (except BDW), Render Cache Operational flush > cannot be enabled. > This WA is apparently required for all Gen4+ platforms,except BDW. > In BDW, the bit has been repurposed otherwise. > This has been tested only on vlv. > > v2: Corrected the code regarding the wrong usage of > MASKED_BIT_DISABLE (Chris) > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) > > v4: Adding WA for g4x, crestline, broadwater (Ville) > > Signed-off-by: Akash Goel <akash.goel@intel.com> > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails the name test anyway). I'm also not a fan of enable(RC_OP_FLUSH_ENABLE)/disable(RC_OP_FLUSH_ENABLE) either, but as far as the content goes, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Sadly, it didn't appear to fix any bugs. -Chris
On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote: > On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta@intel.com wrote: > > From: Akash Goel <akash.goel@intel.com> > > > > On Gen4+ platforms (except BDW), Render Cache Operational flush > > cannot be enabled. > > This WA is apparently required for all Gen4+ platforms,except BDW. > > In BDW, the bit has been repurposed otherwise. > > This has been tested only on vlv. > > > > v2: Corrected the code regarding the wrong usage of > > MASKED_BIT_DISABLE (Chris) > > > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) > > > > v4: Adding WA for g4x, crestline, broadwater (Ville) > > > > Signed-off-by: Akash Goel <akash.goel@intel.com> > > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails > the name test anyway). That's the correct name for the bit on gen3 AFAICS. Might be interesting to try to flip it on gen3 and see if we get moar fps :P > I'm also not a fan of > enable(RC_OP_FLUSH_ENABLE)/disable(RC_OP_FLUSH_ENABLE) either, but as > far as the content goes, > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > Sadly, it didn't appear to fix any bugs. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre
On Fri, Apr 04, 2014 at 06:35:21PM +0300, Ville Syrjälä wrote: > On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote: > > On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta@intel.com wrote: > > > From: Akash Goel <akash.goel@intel.com> > > > > > > On Gen4+ platforms (except BDW), Render Cache Operational flush > > > cannot be enabled. > > > This WA is apparently required for all Gen4+ platforms,except BDW. > > > In BDW, the bit has been repurposed otherwise. > > > This has been tested only on vlv. > > > > > > v2: Corrected the code regarding the wrong usage of > > > MASKED_BIT_DISABLE (Chris) > > > > > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) > > > > > > v4: Adding WA for g4x, crestline, broadwater (Ville) > > > > > > Signed-off-by: Akash Goel <akash.goel@intel.com> > > > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails > > the name test anyway). > > That's the correct name for the bit on gen3 AFAICS. Might be interesting > to try to flip it on gen3 and see if we get moar fps :P Hmm, that's true. Ok, keep the unused name ;-) -Chris
On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote: > On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta@intel.com wrote: > > From: Akash Goel <akash.goel@intel.com> > > > > On Gen4+ platforms (except BDW), Render Cache Operational flush > > cannot be enabled. > > This WA is apparently required for all Gen4+ platforms,except BDW. > > In BDW, the bit has been repurposed otherwise. > > This has been tested only on vlv. > > > > v2: Corrected the code regarding the wrong usage of > > MASKED_BIT_DISABLE (Chris) > > > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) > > > > v4: Adding WA for g4x, crestline, broadwater (Ville) > > > > Signed-off-by: Akash Goel <akash.goel@intel.com> > > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails > the name test anyway). I'm also not a fan of > enable(RC_OP_FLUSH_ENABLE)/disable(RC_OP_FLUSH_ENABLE) either, but as > far as the content goes, > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > Sadly, it didn't appear to fix any bugs. Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 393f93e..366c0bf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1060,6 +1060,7 @@ enum punit_power_well { #define ECO_FLIP_DONE (1<<0) #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ +#define RC_OP_FLUSH_ENABLE (1<<0) #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1454777..17ff36e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4624,6 +4624,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(CACHE_MODE_0, _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); + /* WaDisable_RenderCache_OperationalFlush:ilk */ + I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + g4x_disable_trickle_feed(dev); ibx_init_clock_gating(dev); @@ -4699,6 +4702,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); + /* WaDisable_RenderCache_OperationalFlush:snb */ + I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + /* * BSpec recoomends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. @@ -4938,6 +4944,9 @@ static void haswell_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_FF_THREAD_MODE, I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); + /* WaDisable_RenderCache_OperationalFlush:hsw */ + I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + /* enable HiZ Raw Stall Optimization */ I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); @@ -4990,6 +4999,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* WaDisable_RenderCache_OperationalFlush:ivb */ + I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); @@ -5107,6 +5119,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev) _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* WaDisable_RenderCache_OperationalFlush:vlv */ + I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + /* WaForceL3Serialization:vlv */ I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & ~L3SQ_URB_READ_CAM_MATCH_DISABLE); @@ -5176,6 +5191,9 @@ static void g4x_init_clock_gating(struct drm_device *dev) I915_WRITE(CACHE_MODE_0, _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); + /* WaDisable_RenderCache_OperationalFlush:g4x */ + I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); + g4x_disable_trickle_feed(dev); } @@ -5190,6 +5208,9 @@ static void crestline_init_clock_gating(struct drm_device *dev) I915_WRITE16(DEUC, 0); I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); + + /* WaDisable_RenderCache_OperationalFlush:gen4 */ + I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); } static void broadwater_init_clock_gating(struct drm_device *dev) @@ -5204,6 +5225,9 @@ static void broadwater_init_clock_gating(struct drm_device *dev) I915_WRITE(RENCLK_GATE_D2, 0); I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); + + /* WaDisable_RenderCache_OperationalFlush:gen4 */ + I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); } static void gen3_init_clock_gating(struct drm_device *dev)