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[15/27] ARM: dts: exynos3250: Add uart dt node to support seiral ports

Message ID 1397124377-16969-7-git-send-email-cw00.choi@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chanwoo Choi April 10, 2014, 10:06 a.m. UTC 
This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP
of Exynos4 SoC and has only two independent channels.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[Fix incorrect clock id by Tomasz Figa]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Sachin Kamat April 11, 2014, 4:03 a.m. UTC | #1 
On 10 April 2014 15:36, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP
> of Exynos4 SoC and has only two independent channels.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> [Fix incorrect clock id by Tomasz Figa]
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---

typo in patch subject: s/seiral/serial
Chanwoo Choi April 11, 2014, 4:50 a.m. UTC | #2 
Hi,

On 04/11/2014 01:03 PM, Sachin Kamat wrote:
> On 10 April 2014 15:36, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patch add UART dt node for Exynos3250. Exynos3250 uses same UART IP
>> of Exynos4 SoC and has only two independent channels.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> [Fix incorrect clock id by Tomasz Figa]
>> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>> ---
> 
> typo in patch subject: s/seiral/serial
> 

I'll fix it. Thanks.

Best Regards,
Chanwoo Choi
diff mbox

Patch

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 758913e..d17ed54 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -74,4 +74,22 @@ 
 		reg = <0x11400000 0x1000>;
 		interrupts = <0 240 0>;
 	};
+
+	serial@13800000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13800000 0x100>;
+		interrupts = <0 109 0>;
+		clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
+
+	serial@13810000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x13810000 0x100>;
+		interrupts = <0 110 0>;
+		clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+		clock-names = "uart", "clk_uart_baud0";
+		status = "disabled";
+	};
 };