| Message ID | 1394681222-27882-1-git-send-email-sachin.kamat@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Sachin, On 13.03.2014 04:27, Sachin Kamat wrote: > Set it as per the user manual. > > Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> > --- > drivers/clk/samsung/clk-exynos5420.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 60b26819bed5..7fd6bea467fd 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -33,7 +33,7 @@ > #define RPLL_LOCK 0x10050 > #define IPLL_LOCK 0x10060 > #define SPLL_LOCK 0x10070 > -#define VPLL_LOCK 0x10070 > +#define VPLL_LOCK 0x10080 > #define MPLL_LOCK 0x10090 > #define CPLL_CON0 0x10120 > #define DPLL_CON0 0x10128 > Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate setting on Exynos 5420 (no rate tables registered). Best regards, Tomasz
On 13 March 2014 17:23, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Sachin, > > > On 13.03.2014 04:27, Sachin Kamat wrote: >> >> Set it as per the user manual. >> >> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> >> --- > > Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate > setting on Exynos 5420 (no rate tables registered). Yes, that is correct. Thanks Tomasz.
Hi Tomasz, On 13 March 2014 20:27, Sachin Kamat <sachin.kamat@linaro.org> wrote: > On 13 March 2014 17:23, Tomasz Figa <t.figa@samsung.com> wrote: >> Hi Sachin, >> >> >> On 13.03.2014 04:27, Sachin Kamat wrote: >>> >>> Set it as per the user manual. >>> >>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> >>> --- > >> >> Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate >> setting on Exynos 5420 (no rate tables registered). > > Yes, that is correct. Thanks Tomasz. Looks like this patch hasn't made it to mainline yet.
Hi Sachin, On 01.05.2014 13:10, Sachin Kamat wrote: > Hi Tomasz, > > On 13 March 2014 20:27, Sachin Kamat <sachin.kamat@linaro.org> wrote: >> On 13 March 2014 17:23, Tomasz Figa <t.figa@samsung.com> wrote: >>> Hi Sachin, >>> >>> >>> On 13.03.2014 04:27, Sachin Kamat wrote: >>>> >>>> Set it as per the user manual. >>>> >>>> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> >>>> --- >> >>> >>> Looks fine. Will queue for 3.15, since ATM there is no support for PLL rate >>> setting on Exynos 5420 (no rate tables registered). >> >> Yes, that is correct. Thanks Tomasz. > > Looks like this patch hasn't made it to mainline yet. > Unfortunately that's right. Due to problems with cross tree dependencies there was some fall out and I needed to requeue some patches for 3.16. Sorry for this. Best regards, Tomasz
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 60b26819bed5..7fd6bea467fd 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -33,7 +33,7 @@ #define RPLL_LOCK 0x10050 #define IPLL_LOCK 0x10060 #define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080 #define MPLL_LOCK 0x10090 #define CPLL_CON0 0x10120 #define DPLL_CON0 0x10128
Set it as per the user manual. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)