diff mbox

[v2,1/9] ARM: shmobile: r8a7790: add dmac0,dmac1 clocks

Message ID 1397511312-4845-2-git-send-email-ben.dooks@codethink.co.uk (mailing list archive)
State Rejected
Delegated to: Vinod Koul
Headers show

Commit Message

Ben Dooks April 14, 2014, 9:35 p.m. UTC 
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/arm/boot/dts/r8a7790.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven May 13, 2014, 9:23 a.m. UTC | #1 
Hi Ben,

On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> @@ -671,16 +671,17 @@
>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;

According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
(at 260 MHz), not the HP clock (at 130 MHz).

>                         #clock-cells = <1>;
>                         renesas,clock-indices = <
>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1

I know order doesn't really matter, but all other members are sorted by
value, so R8A7790_CLK_SYS_DMAC1 should come before
R8A7790_CLK_SYS_DMAC0.

>                         >;
>                         clock-output-names =
>                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
> -                               "scifb1", "msiof1", "msiof3", "scifb2";
> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";

"sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
to match the documentation?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Ben Dooks June 4, 2014, 3:54 p.m. UTC | #2 
On 13/05/14 10:23, Geert Uytterhoeven wrote:
> Hi Ben,
> 
> On Mon, Apr 14, 2014 at 11:35 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
>> @@ -671,16 +671,17 @@
>>                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
>>                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
>>                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
>> -                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
>> +                                <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
> 
> According to the docs, the parent clock of SYS-DMAC[01] is the ZS clock
> (at 260 MHz), not the HP clock (at 130 MHz).
> 
>>                         #clock-cells = <1>;
>>                         renesas,clock-indices = <
>>                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
>>                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
>>                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
>> +                               R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
> 
> I know order doesn't really matter, but all other members are sorted by
> value, so R8A7790_CLK_SYS_DMAC1 should come before
> R8A7790_CLK_SYS_DMAC0.
> 
>>                         >;
>>                         clock-output-names =
>>                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
>> -                               "scifb1", "msiof1", "msiof3", "scifb2";
>> +                               "scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
> 
> "sys-dmac0", "sys-dmac1" (and order changes, cfr. my comment above),
> to match the documentation?

ok, thanks.
diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index a1e7c39..f98b01d 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -671,16 +671,17 @@ 
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
-				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&hp_clk>, <&hp_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
 				R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 				R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 				R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+				R8A7790_CLK_SYS_DMAC0 R8A7790_CLK_SYS_DMAC1
 			>;
 			clock-output-names =
 				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
-				"scifb1", "msiof1", "msiof3", "scifb2";
+				"scifb1", "msiof1", "msiof3", "scifb2", "dmac0", "dmac1";
 		};
 		mstp3_clks: mstp3_clks@e615013c {
 			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";