| Message ID | 1400620176-7239-4-git-send-email-robherring2@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Rob, On Tue, May 20, 2014 at 04:09:29PM -0500, Rob Herring wrote: > From: Rob Herring <robh@kernel.org> > > Set the PIC_ENABLES register when the passthru-mask property is present. > This enables interrupts on the secondary controller to be passed thru > directly to the primary controller. > > Signed-off-by: Rob Herring <robh@kernel.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Jason Cooper <jason@lakedaemon.net> > --- > drivers/irqchip/irq-versatile-fpga.c | 6 ++++++ > 1 file changed, 6 insertions(+) Patches 3 and 4 are good to go. Shall I take them, or are they a depended on by later patches? thx, Jason.
On Tue, May 20, 2014 at 8:41 PM, Jason Cooper <jason@lakedaemon.net> wrote: > Rob, > > On Tue, May 20, 2014 at 04:09:29PM -0500, Rob Herring wrote: >> From: Rob Herring <robh@kernel.org> >> >> Set the PIC_ENABLES register when the passthru-mask property is present. >> This enables interrupts on the secondary controller to be passed thru >> directly to the primary controller. >> >> Signed-off-by: Rob Herring <robh@kernel.org> >> Cc: Thomas Gleixner <tglx@linutronix.de> >> Cc: Jason Cooper <jason@lakedaemon.net> >> --- >> drivers/irqchip/irq-versatile-fpga.c | 6 ++++++ >> 1 file changed, 6 insertions(+) > > Patches 3 and 4 are good to go. Shall I take them, or are they a > depended on by later patches? Thanks. There are dependencies, so I plan to send it all thru arm-soc. Rob
On Wed, May 21, 2014 at 10:35:38AM -0500, Rob Herring wrote: > On Tue, May 20, 2014 at 8:41 PM, Jason Cooper <jason@lakedaemon.net> wrote: > > Rob, > > > > On Tue, May 20, 2014 at 04:09:29PM -0500, Rob Herring wrote: > >> From: Rob Herring <robh@kernel.org> > >> > >> Set the PIC_ENABLES register when the passthru-mask property is present. > >> This enables interrupts on the secondary controller to be passed thru > >> directly to the primary controller. > >> > >> Signed-off-by: Rob Herring <robh@kernel.org> > >> Cc: Thomas Gleixner <tglx@linutronix.de> > >> Cc: Jason Cooper <jason@lakedaemon.net> > >> --- > >> drivers/irqchip/irq-versatile-fpga.c | 6 ++++++ > >> 1 file changed, 6 insertions(+) > > > > Patches 3 and 4 are good to go. Shall I take them, or are they a > > depended on by later patches? > > Thanks. There are dependencies, so I plan to send it all thru arm-soc. Very well. For both: Acked-by: Jason Cooper <jason@lakedaemon.net> thx, Jason.
On Tue, May 20, 2014 at 11:09 PM, Rob Herring <robherring2@gmail.com> wrote: > From: Rob Herring <robh@kernel.org> > > Set the PIC_ENABLES register when the passthru-mask property is present. > This enables interrupts on the secondary controller to be passed thru > directly to the primary controller. > > Signed-off-by: Rob Herring <robh@kernel.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Jason Cooper <jason@lakedaemon.net> (...) > +#define PIC_ENABLES 0x20 /* set interrupt pass through bits */ What register is this? In this hardware register 0x20 is #define FIQ_STATUS 0x20 Do you mean that this FPGA IRQ controller is an augmented version with the FIQ portions removed and instead it has some special routing register at 0x20? In that case it should have a different compatible-string should it not? I was under the impression that this was just a simple cascaded IRQ controller cascaded off bit 31 of the VIC, which is much simpler to handle, maybe in the manner of commits e641b987c20832dfaaa51d7792ed928c2b2d2dbf "irqchip: support cascaded VICs" f6da9fe45c3074b909084ae9da5f55034ebffeb4 "irqchip: vic: Properly chain the cascaded IRQs" But for the fpga IRQ driver. Atleast that is how the comments in the device tree says it should work so something is odd here :-/ I really want to know how this special register works. Yours, Linus Walleij
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 3ae2bb8..328440b 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -26,6 +26,8 @@ #define FIQ_ENABLE_SET 0x28 #define FIQ_ENABLE_CLEAR 0x2C +#define PIC_ENABLES 0x20 /* set interrupt pass through bits */ + /** * struct fpga_irq_data - irq data container for the FPGA IRQ controller * @base: memory offset in virtual memory @@ -185,6 +187,7 @@ int __init fpga_irq_of_init(struct device_node *node, void __iomem *base; u32 clear_mask; u32 valid_mask; + u32 passthru_mask; int parent_irq; if (WARN_ON(!node)) @@ -209,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node, writel(clear_mask, base + IRQ_ENABLE_CLEAR); writel(clear_mask, base + FIQ_ENABLE_CLEAR); + if (!of_property_read_u32(node, "passthru-mask", &passthru_mask)) + writel(passthru_mask, base + PIC_ENABLES); + return 0; } #endif