| Message ID | 1400890269-60649-1-git-send-email-Tom.O'Rourke@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 23, 2014 at 05:11:09PM -0700, Tom.O'Rourke@intel.com wrote: > From: Tom O'Rourke <Tom.O'Rourke@intel.com> > > Add Broadwell support to i915_frequency_info and i915_max|min_freq_get|set. > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Many of the checks in here could be simplified to gen >= 6 checks. Would make life easier for the future. -Daniel > --- > drivers/gpu/drm/i915/i915_debugfs.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 333dd12..4d3b7a4 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1027,7 +1027,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > MEMSTAT_VID_SHIFT); > seq_printf(m, "Current P-state: %d\n", > (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); > - } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { > + } else if (IS_GEN6(dev) > + || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) > + || IS_BROADWELL(dev)) { > u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); > u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); > u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); > @@ -1046,7 +1048,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > > reqf = I915_READ(GEN6_RPNSWREQ); > reqf &= ~GEN6_TURBO_DISABLE; > - if (IS_HASWELL(dev)) > + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) > reqf >>= 24; > else > reqf >>= 25; > @@ -1063,7 +1065,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); > rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); > rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); > - if (IS_HASWELL(dev)) > + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; > else > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; > @@ -3500,7 +3502,7 @@ i915_max_freq_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (!(IS_GEN6(dev) || IS_GEN7(dev))) > + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -3526,7 +3528,7 @@ i915_max_freq_set(void *data, u64 val) > u32 rp_state_cap, hw_max, hw_min; > int ret; > > - if (!(IS_GEN6(dev) || IS_GEN7(dev))) > + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -3581,7 +3583,7 @@ i915_min_freq_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (!(IS_GEN6(dev) || IS_GEN7(dev))) > + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -3607,7 +3609,7 @@ i915_min_freq_set(void *data, u64 val) > u32 rp_state_cap, hw_max, hw_min; > int ret; > > - if (!(IS_GEN6(dev) || IS_GEN7(dev))) > + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 333dd12..4d3b7a4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1027,7 +1027,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused) MEMSTAT_VID_SHIFT); seq_printf(m, "Current P-state: %d\n", (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); - } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { + } else if (IS_GEN6(dev) + || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) + || IS_BROADWELL(dev)) { u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); @@ -1046,7 +1048,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) reqf = I915_READ(GEN6_RPNSWREQ); reqf &= ~GEN6_TURBO_DISABLE; - if (IS_HASWELL(dev)) + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) reqf >>= 24; else reqf >>= 25; @@ -1063,7 +1065,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); - if (IS_HASWELL(dev)) + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; else cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; @@ -3500,7 +3502,7 @@ i915_max_freq_get(void *data, u64 *val) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (!(IS_GEN6(dev) || IS_GEN7(dev))) + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -3526,7 +3528,7 @@ i915_max_freq_set(void *data, u64 val) u32 rp_state_cap, hw_max, hw_min; int ret; - if (!(IS_GEN6(dev) || IS_GEN7(dev))) + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -3581,7 +3583,7 @@ i915_min_freq_get(void *data, u64 *val) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (!(IS_GEN6(dev) || IS_GEN7(dev))) + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -3607,7 +3609,7 @@ i915_min_freq_set(void *data, u64 val) u32 rp_state_cap, hw_max, hw_min; int ret; - if (!(IS_GEN6(dev) || IS_GEN7(dev))) + if (!(IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev))) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work);