diff mbox

[6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating

Message ID 1400859021-32202-7-git-send-email-deepak.s@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

deepak.s@linux.intel.com May 23, 2014, 3:30 p.m. UTC 
From: Deepak S <deepak.s@linux.intel.com>

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Mika Kuoppala May 26, 2014, 3:19 p.m. UTC | #1 
deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> [vsyrjala: Fix merge fubmle where the code ended up in
> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 08dcdc5..0b73a6d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>  		   GEN6_RP_UP_BUSY_AVG |
>  		   GEN6_RP_DOWN_IDLE_AVG);
>  
> +	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off
too.

-Mika

>  	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +	case 2:
> +		dev_priv->mem_freq = 1600;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 2000;
> +		break;
> +	}
>  
>  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>  	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter May 27, 2014, 11:42 a.m. UTC | #2 
On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
> deepak.s@linux.intel.com writes:
> 
> > From: Deepak S <deepak.s@linux.intel.com>
> >
> > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > [vsyrjala: Fix merge fubmle where the code ended up in
> > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 08dcdc5..0b73a6d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >  		   GEN6_RP_UP_BUSY_AVG |
> >  		   GEN6_RP_DOWN_IDLE_AVG);
> >  
> > +	/* ToDo: Update the mem freq based on latest spec [CHV]*/
> 
> Please do and consider fixing the vlv decoding. It seems to be off
> too.

Poke about this one here. Iirc the situation on vlv is simply terminal
confusion, and iirc the current code matches reality of shipping vbiosen,
but not any spec. I hope we're bettter for chv.
-Daniel

> 
> -Mika
> 
> >  	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > +	switch ((val >> 6) & 3) {
> > +	case 0:
> > +	case 1:
> > +	case 2:
> > +		dev_priv->mem_freq = 1600;
> > +		break;
> > +	case 3:
> > +		dev_priv->mem_freq = 2000;
> > +		break;
> > +	}
> >  
> >  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> >  	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
> > -- 
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä May 27, 2014, 11:59 a.m. UTC | #3 
On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
> > deepak.s@linux.intel.com writes:
> > 
> > > From: Deepak S <deepak.s@linux.intel.com>
> > >
> > > Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> > > [vsyrjala: Fix merge fubmle where the code ended up in
> > > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 08dcdc5..0b73a6d 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
> > >  		   GEN6_RP_UP_BUSY_AVG |
> > >  		   GEN6_RP_DOWN_IDLE_AVG);
> > >  
> > > +	/* ToDo: Update the mem freq based on latest spec [CHV]*/
> > 
> > Please do and consider fixing the vlv decoding. It seems to be off
> > too.
> 
> Poke about this one here. Iirc the situation on vlv is simply terminal
> confusion, and iirc the current code matches reality of shipping vbiosen,
> but not any spec.

Yeah changed back here:

commit f6d519481b662d9fc52836e6e6107520f03e0122
Author: Deepak S <deepak.s@linux.intel.com>
Date:   Thu Apr 3 21:01:28 2014 +0530

    Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
    
    As per the inputs provided by hardware team  we still use DDR
    Rates as 0,1=800, 2=1066, 3=1333.
    With this change, Turbo freqs used on current machines matches.


I think what we need is a comment there which states why
we're going against the spec, just to avoid future confusion
and someone accidentally changing it back again.

> I hope we're bettter for chv.

One can dream.
deepak.s@linux.intel.com May 27, 2014, 12:11 p.m. UTC | #4 
On Tuesday 27 May 2014 05:29 PM, Ville Syrjälä wrote:
> On Tue, May 27, 2014 at 01:42:50PM +0200, Daniel Vetter wrote:
>> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
>>> deepak.s@linux.intel.com writes:
>>>
>>>> From: Deepak S <deepak.s@linux.intel.com>
>>>>
>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>>> [vsyrjala: Fix merge fubmle where the code ended up in
>>>> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
>>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> Acked-by: Ben Widawsky <ben@bwidawsk.net>
>>>> ---
>>>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>>   1 file changed, 11 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index 08dcdc5..0b73a6d 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>>   		   GEN6_RP_UP_BUSY_AVG |
>>>>   		   GEN6_RP_DOWN_IDLE_AVG);
>>>>   
>>>> +	/* ToDo: Update the mem freq based on latest spec [CHV]*/
>>> Please do and consider fixing the vlv decoding. It seems to be off
>>> too.
>> Poke about this one here. Iirc the situation on vlv is simply terminal
>> confusion, and iirc the current code matches reality of shipping vbiosen,
>> but not any spec.
> Yeah changed back here:
>
> commit f6d519481b662d9fc52836e6e6107520f03e0122
> Author: Deepak S <deepak.s@linux.intel.com>
> Date:   Thu Apr 3 21:01:28 2014 +0530
>
>      Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"
>      
>      As per the inputs provided by hardware team  we still use DDR
>      Rates as 0,1=800, 2=1066, 3=1333.
>      With this change, Turbo freqs used on current machines matches.
>
>
> I think what we need is a comment there which states why
> we're going against the spec, just to avoid future confusion
> and someone accidentally changing it back again.
>
>> I hope we're bettter for chv.
> One can dream.

Problem is the spec is not update to latest. Based on the communication from the HW team i update the proper value.
For CHV, I have updated based on the values i got from HW team.
deepak.s@linux.intel.com May 27, 2014, 12:13 p.m. UTC | #5 
On Tuesday 27 May 2014 05:12 PM, Daniel Vetter wrote:
> On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote:
>> deepak.s@linux.intel.com writes:
>>
>>> From: Deepak S <deepak.s@linux.intel.com>
>>>
>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>>> [vsyrjala: Fix merge fubmle where the code ended up in
>>> g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Acked-by: Ben Widawsky <ben@bwidawsk.net>
>>> ---
>>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>>   1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index 08dcdc5..0b73a6d 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
>>>   		   GEN6_RP_UP_BUSY_AVG |
>>>   		   GEN6_RP_DOWN_IDLE_AVG);
>>>   
>>> +	/* ToDo: Update the mem freq based on latest spec [CHV]*/
>> Please do and consider fixing the vlv decoding. It seems to be off
>> too.
> Poke about this one here. Iirc the situation on vlv is simply terminal
> confusion, and iirc the current code matches reality of shipping vbiosen,
> but not any spec. I hope we're bettter for chv.
> -Daniel

I am trying to get proper values updated in the spec so that we dont have confusion. Once it is available I will update the code accordingly.

>> -Mika
>>
>>>   	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>>> +	switch ((val >> 6) & 3) {
>>> +	case 0:
>>> +	case 1:
>>> +	case 2:
>>> +		dev_priv->mem_freq = 1600;
>>> +		break;
>>> +	case 3:
>>> +		dev_priv->mem_freq = 2000;
>>> +		break;
>>> +	}
>>>   
>>>   	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
>>>   	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>>> -- 
>>> 1.9.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08dcdc5..0b73a6d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4026,7 +4026,18 @@  static void cherryview_enable_rps(struct drm_device *dev)
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 
+	/* ToDo: Update the mem freq based on latest spec [CHV]*/
 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+	case 2:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
 
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
 	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);