| Message ID | 1401098197-647-4-git-send-email-j-keerthy@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> Add tps65917 specific definitions and enums. > > Signed-off-by: Keerthy <j-keerthy@ti.com> > --- > include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 793 insertions(+) Looks okay to me: Acked-by: Lee Jones <lee.jones@linaro.org> Do the MFD patches have dependencies or are they depended on by the others in the set? > diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h > index ccbb21f..52a24a9 100644 > --- a/include/linux/mfd/palmas.h > +++ b/include/linux/mfd/palmas.h > @@ -30,6 +30,8 @@ > #define PALMAS_CHIP_ID 0xC035 > #define PALMAS_CHIP_CHARGER_ID 0xC036 > > +#define TPS65917_RESERVED -1 > + > #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ > ((a) == PALMAS_CHIP_ID)) > #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) > @@ -184,6 +186,27 @@ enum palmas_regulators { > PALMAS_NUM_REGS, > }; > > +enum tps65917_regulators { > + /* SMPS regulators */ > + TPS65917_REG_SMPS1, > + TPS65917_REG_SMPS2, > + TPS65917_REG_SMPS3, > + TPS65917_REG_SMPS4, > + TPS65917_REG_SMPS5, > + /* LDO regulators */ > + TPS65917_REG_LDO1, > + TPS65917_REG_LDO2, > + TPS65917_REG_LDO3, > + TPS65917_REG_LDO4, > + TPS65917_REG_LDO5, > + TPS65917_REG_REGEN1, > + TPS65917_REG_REGEN2, > + TPS65917_REG_REGEN3, > + > + /* Total number of regulators */ > + TPS65917_NUM_REGS, > +}; > + > /* External controll signal name */ > enum { > PALMAS_EXT_CONTROL_ENABLE1 = 0x1, > @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { > PALMAS_EXTERNAL_REQSTR_ID_MAX, > }; > > +enum tps65917_external_requestor_id { > + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, > + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, > + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, > + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, > + TPS65917_EXTERNAL_REQSTR_ID_LDO1, > + TPS65917_EXTERNAL_REQSTR_ID_LDO2, > + TPS65917_EXTERNAL_REQSTR_ID_LDO3, > + TPS65917_EXTERNAL_REQSTR_ID_LDO4, > + TPS65917_EXTERNAL_REQSTR_ID_LDO5, > + /* Last entry */ > + TPS65917_EXTERNAL_REQSTR_ID_MAX, > +}; > + > struct palmas_pmic_platform_data { > /* An array of pointers to regulator init data indexed by regulator > * ID > @@ -349,6 +390,48 @@ struct palmas_gpadc_result { > > #define PALMAS_MAX_CHANNELS 16 > > +/* Define the tps65917 IRQ numbers */ > +enum tps65917_irqs { > + /* INT1 registers */ > + TPS65917_RESERVED1, > + TPS65917_PWRON_IRQ, > + TPS65917_LONG_PRESS_KEY_IRQ, > + TPS65917_RESERVED2, > + TPS65917_PWRDOWN_IRQ, > + TPS65917_HOTDIE_IRQ, > + TPS65917_VSYS_MON_IRQ, > + TPS65917_RESERVED3, > + /* INT2 registers */ > + TPS65917_RESERVED4, > + TPS65917_OTP_ERROR_IRQ, > + TPS65917_WDT_IRQ, > + TPS65917_RESERVED5, > + TPS65917_RESET_IN_IRQ, > + TPS65917_FSD_IRQ, > + TPS65917_SHORT_IRQ, > + TPS65917_RESERVED6, > + /* INT3 registers */ > + TPS65917_GPADC_AUTO_0_IRQ, > + TPS65917_GPADC_AUTO_1_IRQ, > + TPS65917_GPADC_EOC_SW_IRQ, > + TPS65917_RESREVED6, > + TPS65917_RESERVED7, > + TPS65917_RESERVED8, > + TPS65917_RESERVED9, > + TPS65917_VBUS_IRQ, > + /* INT4 registers */ > + TPS65917_GPIO_0_IRQ, > + TPS65917_GPIO_1_IRQ, > + TPS65917_GPIO_2_IRQ, > + TPS65917_GPIO_3_IRQ, > + TPS65917_GPIO_4_IRQ, > + TPS65917_GPIO_5_IRQ, > + TPS65917_GPIO_6_IRQ, > + TPS65917_RESERVED10, > + /* Total Number IRQs */ > + TPS65917_NUM_IRQ, > +}; > + > /* Define the palmas IRQ numbers */ > enum palmas_irqs { > /* INT1 registers */ > @@ -400,6 +483,7 @@ struct palmas_pmic { > > int smps123; > int smps457; > + int smps12; > > int range[PALMAS_REG_SMPS10_OUT1]; > unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; > @@ -2871,6 +2955,715 @@ enum usb_irq_events { > #define PALMAS_GPADC_TRIM15 0x0E > #define PALMAS_GPADC_TRIM16 0x0F > > +/* TPS65917 Interrupt registers */ > + > +/* Registers for function INTERRUPT */ > +#define TPS65917_INT1_STATUS 0x00 > +#define TPS65917_INT1_MASK 0x01 > +#define TPS65917_INT1_LINE_STATE 0x02 > +#define TPS65917_INT2_STATUS 0x05 > +#define TPS65917_INT2_MASK 0x06 > +#define TPS65917_INT2_LINE_STATE 0x07 > +#define TPS65917_INT3_STATUS 0x0A > +#define TPS65917_INT3_MASK 0x0B > +#define TPS65917_INT3_LINE_STATE 0x0C > +#define TPS65917_INT4_STATUS 0x0F > +#define TPS65917_INT4_MASK 0x10 > +#define TPS65917_INT4_LINE_STATE 0x11 > +#define TPS65917_INT4_EDGE_DETECT1 0x12 > +#define TPS65917_INT4_EDGE_DETECT2 0x13 > +#define TPS65917_INT_CTRL 0x14 > + > +/* Bit definitions for INT1_STATUS */ > +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 > +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_STATUS_HOTDIE 0x20 > +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 > +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_STATUS_PWRON 0x02 > +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT1_MASK */ > +#define TPS65917_INT1_MASK_VSYS_MON 0x40 > +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_MASK_HOTDIE 0x20 > +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_MASK_PWRDOWN 0x10 > +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_MASK_PWRON 0x02 > +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT1_LINE_STATE */ > +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 > +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 > +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 > +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 > +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 > +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 > +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 > +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 > +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 > +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 > + > +/* Bit definitions for INT2_STATUS */ > +#define TPS65917_INT2_STATUS_SHORT 0x40 > +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_STATUS_FSD 0x20 > +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 > +#define TPS65917_INT2_STATUS_RESET_IN 0x10 > +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_STATUS_WDT 0x04 > +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 > +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 > +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT2_MASK */ > +#define TPS65917_INT2_MASK_SHORT 0x40 > +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_MASK_FSD 0x20 > +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 > +#define TPS65917_INT2_MASK_RESET_IN 0x10 > +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_MASK_WDT 0x04 > +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 > +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 > +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT2_LINE_STATE */ > +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 > +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 > +#define TPS65917_INT2_LINE_STATE_FSD 0x20 > +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 > +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 > +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 > +#define TPS65917_INT2_LINE_STATE_WDT 0x04 > +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 > +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 > +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 > + > +/* Bit definitions for INT3_STATUS */ > +#define TPS65917_INT3_STATUS_VBUS 0x80 > +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT3_MASK */ > +#define TPS65917_INT3_MASK_VBUS 0x80 > +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT3_LINE_STATE */ > +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 > +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 > +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 > +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 > +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_STATUS */ > +#define TPS65917_INT4_STATUS_GPIO_6 0x40 > +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_STATUS_GPIO_5 0x20 > +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_STATUS_GPIO_4 0x10 > +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_STATUS_GPIO_3 0x08 > +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_STATUS_GPIO_2 0x04 > +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_STATUS_GPIO_1 0x02 > +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_STATUS_GPIO_0 0x01 > +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_MASK */ > +#define TPS65917_INT4_MASK_GPIO_6 0x40 > +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_MASK_GPIO_5 0x20 > +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_MASK_GPIO_4 0x10 > +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_MASK_GPIO_3 0x08 > +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_MASK_GPIO_2 0x04 > +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_MASK_GPIO_1 0x02 > +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_MASK_GPIO_0 0x01 > +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_LINE_STATE */ > +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 > +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 > +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 > +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 > +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 > +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 > +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 > +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 > +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 > +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 > +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 > +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 > +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 > +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 > + > +/* Bit definitions for INT4_EDGE_DETECT1 */ > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 > +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 > + > +/* Bit definitions for INT4_EDGE_DETECT2 */ > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 > +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 > + > +/* Bit definitions for INT_CTRL */ > +#define TPS65917_INT_CTRL_INT_PENDING 0x04 > +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 > +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 > +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 > + > +/* TPS65917 SMPS Registers */ > + > +/* Registers for function SMPS */ > +#define TPS65917_SMPS1_CTRL 0x00 > +#define TPS65917_SMPS1_FORCE 0x02 > +#define TPS65917_SMPS1_VOLTAGE 0x03 > +#define TPS65917_SMPS2_CTRL 0x04 > +#define TPS65917_SMPS2_FORCE 0x06 > +#define TPS65917_SMPS2_VOLTAGE 0x07 > +#define TPS65917_SMPS3_CTRL 0x0C > +#define TPS65917_SMPS3_FORCE 0x0E > +#define TPS65917_SMPS3_VOLTAGE 0x0F > +#define TPS65917_SMPS4_CTRL 0x10 > +#define TPS65917_SMPS4_VOLTAGE 0x13 > +#define TPS65917_SMPS5_CTRL 0x18 > +#define TPS65917_SMPS5_VOLTAGE 0x1B > +#define TPS65917_SMPS_CTRL 0x24 > +#define TPS65917_SMPS_PD_CTRL 0x25 > +#define TPS65917_SMPS_THERMAL_EN 0x27 > +#define TPS65917_SMPS_THERMAL_STATUS 0x28 > +#define TPS65917_SMPS_SHORT_STATUS 0x29 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A > +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B > +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C > + > +/* Bit definitions for SMPS1_CTRL */ > +#define TPS65917_SMPS1_CTRL_WR_S 0x80 > +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS1_FORCE */ > +#define TPS65917_SMPS1_FORCE_CMD 0x80 > +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS1_VOLTAGE */ > +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_CTRL */ > +#define TPS65917_SMPS2_CTRL_WR_S 0x80 > +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_FORCE */ > +#define TPS65917_SMPS2_FORCE_CMD 0x80 > +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS2_VOLTAGE */ > +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_CTRL */ > +#define TPS65917_SMPS3_CTRL_WR_S 0x80 > +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_FORCE */ > +#define TPS65917_SMPS3_FORCE_CMD 0x80 > +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 > +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F > +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS3_VOLTAGE */ > +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS4_CTRL */ > +#define TPS65917_SMPS4_CTRL_WR_S 0x80 > +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS4_VOLTAGE */ > +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS5_CTRL */ > +#define TPS65917_SMPS5_CTRL_WR_S 0x80 > +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 > +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 > +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 > +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C > +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 > +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for SMPS5_VOLTAGE */ > +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 > +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 > +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F > +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for SMPS_CTRL */ > +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 > +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 > +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 > +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 > + > +/* Bit definitions for SMPS_PD_CTRL */ > +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 > +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 > +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 > +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 > +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 > +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_THERMAL_EN */ > +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 > +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 > +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 > +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 > + > +/* Bit definitions for SMPS_THERMAL_STATUS */ > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 > +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 > + > +/* Bit definitions for SMPS_SHORT_STATUS */ > +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 > +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 > +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 > +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ > +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 > +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 > +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 > +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 > + > +/* Bit definitions for SMPS_PLL_CTRL */ > + > +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 > +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 > + > +/* Registers for function LDO */ > +#define TPS65917_LDO1_CTRL 0x00 > +#define TPS65917_LDO1_VOLTAGE 0x01 > +#define TPS65917_LDO2_CTRL 0x02 > +#define TPS65917_LDO2_VOLTAGE 0x03 > +#define TPS65917_LDO3_CTRL 0x04 > +#define TPS65917_LDO3_VOLTAGE 0x05 > +#define TPS65917_LDO4_CTRL 0x0E > +#define TPS65917_LDO4_VOLTAGE 0x0F > +#define TPS65917_LDO5_CTRL 0x12 > +#define TPS65917_LDO5_VOLTAGE 0x13 > +#define TPS65917_LDO_PD_CTRL1 0x1B > +#define TPS65917_LDO_PD_CTRL2 0x1C > +#define TPS65917_LDO_SHORT_STATUS1 0x1D > +#define TPS65917_LDO_SHORT_STATUS2 0x1E > +#define TPS65917_LDO_PD_CTRL3 0x2D > +#define TPS65917_LDO_SHORT_STATUS3 0x2E > + > +/* Bit definitions for LDO1_CTRL */ > +#define TPS65917_LDO1_CTRL_WR_S 0x80 > +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 > +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 > +#define TPS65917_LDO1_CTRL_STATUS 0x10 > +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO1_VOLTAGE */ > +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO2_CTRL */ > +#define TPS65917_LDO2_CTRL_WR_S 0x80 > +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 > +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 > +#define TPS65917_LDO2_CTRL_STATUS 0x10 > +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO2_VOLTAGE */ > +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO3_CTRL */ > +#define TPS65917_LDO3_CTRL_WR_S 0x80 > +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO3_CTRL_STATUS 0x10 > +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO3_VOLTAGE */ > +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO4_CTRL */ > +#define TPS65917_LDO4_CTRL_WR_S 0x80 > +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO4_CTRL_STATUS 0x10 > +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO4_VOLTAGE */ > +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO5_CTRL */ > +#define TPS65917_LDO5_CTRL_WR_S 0x80 > +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 > +#define TPS65917_LDO5_CTRL_STATUS 0x10 > +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for LDO5_VOLTAGE */ > +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F > +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 > + > +/* Bit definitions for LDO_PD_CTRL1 */ > +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 > +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 > +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 > +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 > +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 > +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for LDO_PD_CTRL2 */ > +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 > +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 > +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 > +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for LDO_PD_CTRL3 */ > +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 > +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 > + > +/* Bit definitions for LDO_SHORT_STATUS1 */ > +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 > +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 > +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 > +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 > +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 > +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for LDO_SHORT_STATUS2 */ > +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 > +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 > +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 > +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for LDO_SHORT_STATUS2 */ > +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 > +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 > + > +/* Bit definitions for REGEN1_CTRL */ > +#define TPS65917_REGEN1_CTRL_STATUS 0x10 > +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for PLLEN_CTRL */ > +#define TPS65917_PLLEN_CTRL_STATUS 0x10 > +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for REGEN2_CTRL */ > +#define TPS65917_REGEN2_CTRL_STATUS 0x10 > +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_RES_ASSIGN */ > +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 > +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for ENABLE1_RES_ASSIGN */ > +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 > +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for ENABLE2_RES_ASSIGN */ > +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 > +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 > +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 > +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 > +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 > + > +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 > +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 > + > +/* Bit definitions for REGEN3_CTRL */ > +#define TPS65917_REGEN3_CTRL_STATUS 0x10 > +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 > +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 > +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 > +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 > +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 > + > +/* Registers for function RESOURCE */ > +#define TPS65917_REGEN1_CTRL 0x2 > +#define TPS65917_PLLEN_CTRL 0x3 > +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 > +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 > +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 > +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 > +#define TPS65917_ENABLE1_RES_ASSIGN 0xA > +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB > +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC > +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD > +#define TPS65917_ENABLE2_RES_ASSIGN 0xE > +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF > +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 > +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 > +#define TPS65917_REGEN2_CTRL 0x12 > +#define TPS65917_REGEN3_CTRL 0x13 > + > static inline int palmas_read(struct palmas *palmas, unsigned int base, > unsigned int reg, unsigned int *val) > {
On Tuesday 27 May 2014 02:11 PM, Lee Jones wrote: >> Add tps65917 specific definitions and enums. >> >> Signed-off-by: Keerthy <j-keerthy@ti.com> >> --- >> include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 793 insertions(+) > Looks okay to me: > > Acked-by: Lee Jones <lee.jones@linaro.org> > > Do the MFD patches have dependencies or are they depended on by the > others in the set? No Dependency as such. These can be applied independently. I will work on unifying the regulator driver for palmas and tps65917. > >> diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h >> index ccbb21f..52a24a9 100644 >> --- a/include/linux/mfd/palmas.h >> +++ b/include/linux/mfd/palmas.h >> @@ -30,6 +30,8 @@ >> #define PALMAS_CHIP_ID 0xC035 >> #define PALMAS_CHIP_CHARGER_ID 0xC036 >> >> +#define TPS65917_RESERVED -1 >> + >> #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ >> ((a) == PALMAS_CHIP_ID)) >> #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) >> @@ -184,6 +186,27 @@ enum palmas_regulators { >> PALMAS_NUM_REGS, >> }; >> >> +enum tps65917_regulators { >> + /* SMPS regulators */ >> + TPS65917_REG_SMPS1, >> + TPS65917_REG_SMPS2, >> + TPS65917_REG_SMPS3, >> + TPS65917_REG_SMPS4, >> + TPS65917_REG_SMPS5, >> + /* LDO regulators */ >> + TPS65917_REG_LDO1, >> + TPS65917_REG_LDO2, >> + TPS65917_REG_LDO3, >> + TPS65917_REG_LDO4, >> + TPS65917_REG_LDO5, >> + TPS65917_REG_REGEN1, >> + TPS65917_REG_REGEN2, >> + TPS65917_REG_REGEN3, >> + >> + /* Total number of regulators */ >> + TPS65917_NUM_REGS, >> +}; >> + >> /* External controll signal name */ >> enum { >> PALMAS_EXT_CONTROL_ENABLE1 = 0x1, >> @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { >> PALMAS_EXTERNAL_REQSTR_ID_MAX, >> }; >> >> +enum tps65917_external_requestor_id { >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, >> + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, >> + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO1, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO2, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO3, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO4, >> + TPS65917_EXTERNAL_REQSTR_ID_LDO5, >> + /* Last entry */ >> + TPS65917_EXTERNAL_REQSTR_ID_MAX, >> +}; >> + >> struct palmas_pmic_platform_data { >> /* An array of pointers to regulator init data indexed by regulator >> * ID >> @@ -349,6 +390,48 @@ struct palmas_gpadc_result { >> >> #define PALMAS_MAX_CHANNELS 16 >> >> +/* Define the tps65917 IRQ numbers */ >> +enum tps65917_irqs { >> + /* INT1 registers */ >> + TPS65917_RESERVED1, >> + TPS65917_PWRON_IRQ, >> + TPS65917_LONG_PRESS_KEY_IRQ, >> + TPS65917_RESERVED2, >> + TPS65917_PWRDOWN_IRQ, >> + TPS65917_HOTDIE_IRQ, >> + TPS65917_VSYS_MON_IRQ, >> + TPS65917_RESERVED3, >> + /* INT2 registers */ >> + TPS65917_RESERVED4, >> + TPS65917_OTP_ERROR_IRQ, >> + TPS65917_WDT_IRQ, >> + TPS65917_RESERVED5, >> + TPS65917_RESET_IN_IRQ, >> + TPS65917_FSD_IRQ, >> + TPS65917_SHORT_IRQ, >> + TPS65917_RESERVED6, >> + /* INT3 registers */ >> + TPS65917_GPADC_AUTO_0_IRQ, >> + TPS65917_GPADC_AUTO_1_IRQ, >> + TPS65917_GPADC_EOC_SW_IRQ, >> + TPS65917_RESREVED6, >> + TPS65917_RESERVED7, >> + TPS65917_RESERVED8, >> + TPS65917_RESERVED9, >> + TPS65917_VBUS_IRQ, >> + /* INT4 registers */ >> + TPS65917_GPIO_0_IRQ, >> + TPS65917_GPIO_1_IRQ, >> + TPS65917_GPIO_2_IRQ, >> + TPS65917_GPIO_3_IRQ, >> + TPS65917_GPIO_4_IRQ, >> + TPS65917_GPIO_5_IRQ, >> + TPS65917_GPIO_6_IRQ, >> + TPS65917_RESERVED10, >> + /* Total Number IRQs */ >> + TPS65917_NUM_IRQ, >> +}; >> + >> /* Define the palmas IRQ numbers */ >> enum palmas_irqs { >> /* INT1 registers */ >> @@ -400,6 +483,7 @@ struct palmas_pmic { >> >> int smps123; >> int smps457; >> + int smps12; >> >> int range[PALMAS_REG_SMPS10_OUT1]; >> unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; >> @@ -2871,6 +2955,715 @@ enum usb_irq_events { >> #define PALMAS_GPADC_TRIM15 0x0E >> #define PALMAS_GPADC_TRIM16 0x0F >> >> +/* TPS65917 Interrupt registers */ >> + >> +/* Registers for function INTERRUPT */ >> +#define TPS65917_INT1_STATUS 0x00 >> +#define TPS65917_INT1_MASK 0x01 >> +#define TPS65917_INT1_LINE_STATE 0x02 >> +#define TPS65917_INT2_STATUS 0x05 >> +#define TPS65917_INT2_MASK 0x06 >> +#define TPS65917_INT2_LINE_STATE 0x07 >> +#define TPS65917_INT3_STATUS 0x0A >> +#define TPS65917_INT3_MASK 0x0B >> +#define TPS65917_INT3_LINE_STATE 0x0C >> +#define TPS65917_INT4_STATUS 0x0F >> +#define TPS65917_INT4_MASK 0x10 >> +#define TPS65917_INT4_LINE_STATE 0x11 >> +#define TPS65917_INT4_EDGE_DETECT1 0x12 >> +#define TPS65917_INT4_EDGE_DETECT2 0x13 >> +#define TPS65917_INT_CTRL 0x14 >> + >> +/* Bit definitions for INT1_STATUS */ >> +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 >> +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_STATUS_HOTDIE 0x20 >> +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 >> +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_STATUS_PWRON 0x02 >> +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT1_MASK */ >> +#define TPS65917_INT1_MASK_VSYS_MON 0x40 >> +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_MASK_HOTDIE 0x20 >> +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_MASK_PWRDOWN 0x10 >> +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_MASK_PWRON 0x02 >> +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT1_LINE_STATE */ >> +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 >> +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 >> +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 >> +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 >> +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 >> +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 >> +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 >> +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 >> +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 >> +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_STATUS */ >> +#define TPS65917_INT2_STATUS_SHORT 0x40 >> +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_STATUS_FSD 0x20 >> +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_STATUS_RESET_IN 0x10 >> +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_STATUS_WDT 0x04 >> +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 >> +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_MASK */ >> +#define TPS65917_INT2_MASK_SHORT 0x40 >> +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_MASK_FSD 0x20 >> +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_MASK_RESET_IN 0x10 >> +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_MASK_WDT 0x04 >> +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 >> +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT2_LINE_STATE */ >> +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 >> +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 >> +#define TPS65917_INT2_LINE_STATE_FSD 0x20 >> +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 >> +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 >> +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 >> +#define TPS65917_INT2_LINE_STATE_WDT 0x04 >> +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 >> +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 >> +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 >> + >> +/* Bit definitions for INT3_STATUS */ >> +#define TPS65917_INT3_STATUS_VBUS 0x80 >> +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT3_MASK */ >> +#define TPS65917_INT3_MASK_VBUS 0x80 >> +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT3_LINE_STATE */ >> +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 >> +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 >> +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 >> +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 >> +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_STATUS */ >> +#define TPS65917_INT4_STATUS_GPIO_6 0x40 >> +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_STATUS_GPIO_5 0x20 >> +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_STATUS_GPIO_4 0x10 >> +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_STATUS_GPIO_3 0x08 >> +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_STATUS_GPIO_2 0x04 >> +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_STATUS_GPIO_1 0x02 >> +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_STATUS_GPIO_0 0x01 >> +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_MASK */ >> +#define TPS65917_INT4_MASK_GPIO_6 0x40 >> +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_MASK_GPIO_5 0x20 >> +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_MASK_GPIO_4 0x10 >> +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_MASK_GPIO_3 0x08 >> +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_MASK_GPIO_2 0x04 >> +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_MASK_GPIO_1 0x02 >> +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_MASK_GPIO_0 0x01 >> +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_LINE_STATE */ >> +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 >> +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 >> +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 >> +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 >> +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 >> +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 >> +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 >> +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 >> +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 >> +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 >> +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 >> +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 >> +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 >> +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_EDGE_DETECT1 */ >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 >> +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 >> + >> +/* Bit definitions for INT4_EDGE_DETECT2 */ >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 >> +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 >> + >> +/* Bit definitions for INT_CTRL */ >> +#define TPS65917_INT_CTRL_INT_PENDING 0x04 >> +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 >> +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 >> +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 >> + >> +/* TPS65917 SMPS Registers */ >> + >> +/* Registers for function SMPS */ >> +#define TPS65917_SMPS1_CTRL 0x00 >> +#define TPS65917_SMPS1_FORCE 0x02 >> +#define TPS65917_SMPS1_VOLTAGE 0x03 >> +#define TPS65917_SMPS2_CTRL 0x04 >> +#define TPS65917_SMPS2_FORCE 0x06 >> +#define TPS65917_SMPS2_VOLTAGE 0x07 >> +#define TPS65917_SMPS3_CTRL 0x0C >> +#define TPS65917_SMPS3_FORCE 0x0E >> +#define TPS65917_SMPS3_VOLTAGE 0x0F >> +#define TPS65917_SMPS4_CTRL 0x10 >> +#define TPS65917_SMPS4_VOLTAGE 0x13 >> +#define TPS65917_SMPS5_CTRL 0x18 >> +#define TPS65917_SMPS5_VOLTAGE 0x1B >> +#define TPS65917_SMPS_CTRL 0x24 >> +#define TPS65917_SMPS_PD_CTRL 0x25 >> +#define TPS65917_SMPS_THERMAL_EN 0x27 >> +#define TPS65917_SMPS_THERMAL_STATUS 0x28 >> +#define TPS65917_SMPS_SHORT_STATUS 0x29 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A >> +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B >> +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C >> + >> +/* Bit definitions for SMPS1_CTRL */ >> +#define TPS65917_SMPS1_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS1_FORCE */ >> +#define TPS65917_SMPS1_FORCE_CMD 0x80 >> +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS1_VOLTAGE */ >> +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_CTRL */ >> +#define TPS65917_SMPS2_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_FORCE */ >> +#define TPS65917_SMPS2_FORCE_CMD 0x80 >> +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS2_VOLTAGE */ >> +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_CTRL */ >> +#define TPS65917_SMPS3_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_FORCE */ >> +#define TPS65917_SMPS3_FORCE_CMD 0x80 >> +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 >> +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS3_VOLTAGE */ >> +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS4_CTRL */ >> +#define TPS65917_SMPS4_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS4_VOLTAGE */ >> +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS5_CTRL */ >> +#define TPS65917_SMPS5_CTRL_WR_S 0x80 >> +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 >> +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 >> +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 >> +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C >> +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 >> +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS5_VOLTAGE */ >> +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 >> +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 >> +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F >> +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_CTRL */ >> +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 >> +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 >> +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 >> +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_PD_CTRL */ >> +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 >> +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 >> +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 >> +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 >> +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 >> +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_THERMAL_EN */ >> +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 >> +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_THERMAL_STATUS */ >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 >> +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_SHORT_STATUS */ >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 >> +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 >> +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 >> +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ >> +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 >> +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 >> + >> +/* Bit definitions for SMPS_PLL_CTRL */ >> + >> +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 >> +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 >> + >> +/* Registers for function LDO */ >> +#define TPS65917_LDO1_CTRL 0x00 >> +#define TPS65917_LDO1_VOLTAGE 0x01 >> +#define TPS65917_LDO2_CTRL 0x02 >> +#define TPS65917_LDO2_VOLTAGE 0x03 >> +#define TPS65917_LDO3_CTRL 0x04 >> +#define TPS65917_LDO3_VOLTAGE 0x05 >> +#define TPS65917_LDO4_CTRL 0x0E >> +#define TPS65917_LDO4_VOLTAGE 0x0F >> +#define TPS65917_LDO5_CTRL 0x12 >> +#define TPS65917_LDO5_VOLTAGE 0x13 >> +#define TPS65917_LDO_PD_CTRL1 0x1B >> +#define TPS65917_LDO_PD_CTRL2 0x1C >> +#define TPS65917_LDO_SHORT_STATUS1 0x1D >> +#define TPS65917_LDO_SHORT_STATUS2 0x1E >> +#define TPS65917_LDO_PD_CTRL3 0x2D >> +#define TPS65917_LDO_SHORT_STATUS3 0x2E >> + >> +/* Bit definitions for LDO1_CTRL */ >> +#define TPS65917_LDO1_CTRL_WR_S 0x80 >> +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 >> +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 >> +#define TPS65917_LDO1_CTRL_STATUS 0x10 >> +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO1_VOLTAGE */ >> +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO2_CTRL */ >> +#define TPS65917_LDO2_CTRL_WR_S 0x80 >> +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 >> +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 >> +#define TPS65917_LDO2_CTRL_STATUS 0x10 >> +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO2_VOLTAGE */ >> +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO3_CTRL */ >> +#define TPS65917_LDO3_CTRL_WR_S 0x80 >> +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO3_CTRL_STATUS 0x10 >> +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO3_VOLTAGE */ >> +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO4_CTRL */ >> +#define TPS65917_LDO4_CTRL_WR_S 0x80 >> +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO4_CTRL_STATUS 0x10 >> +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO4_VOLTAGE */ >> +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO5_CTRL */ >> +#define TPS65917_LDO5_CTRL_WR_S 0x80 >> +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 >> +#define TPS65917_LDO5_CTRL_STATUS 0x10 >> +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for LDO5_VOLTAGE */ >> +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F >> +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_PD_CTRL1 */ >> +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 >> +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 >> +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 >> +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 >> +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 >> +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_PD_CTRL2 */ >> +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 >> +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 >> +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 >> +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for LDO_PD_CTRL3 */ >> +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 >> +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 >> + >> +/* Bit definitions for LDO_SHORT_STATUS1 */ >> +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 >> +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for LDO_SHORT_STATUS2 */ >> +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 >> +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for LDO_SHORT_STATUS2 */ >> +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 >> +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 >> + >> +/* Bit definitions for REGEN1_CTRL */ >> +#define TPS65917_REGEN1_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for PLLEN_CTRL */ >> +#define TPS65917_PLLEN_CTRL_STATUS 0x10 >> +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for REGEN2_CTRL */ >> +#define TPS65917_REGEN2_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_RES_ASSIGN */ >> +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 >> +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for ENABLE1_RES_ASSIGN */ >> +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 >> +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for ENABLE2_RES_ASSIGN */ >> +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 >> +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 >> +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 >> +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 >> +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 >> + >> +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 >> + >> +/* Bit definitions for REGEN3_CTRL */ >> +#define TPS65917_REGEN3_CTRL_STATUS 0x10 >> +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 >> +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 >> +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 >> +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 >> +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 >> + >> +/* Registers for function RESOURCE */ >> +#define TPS65917_REGEN1_CTRL 0x2 >> +#define TPS65917_PLLEN_CTRL 0x3 >> +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 >> +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 >> +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 >> +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 >> +#define TPS65917_ENABLE1_RES_ASSIGN 0xA >> +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB >> +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC >> +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD >> +#define TPS65917_ENABLE2_RES_ASSIGN 0xE >> +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF >> +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 >> +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 >> +#define TPS65917_REGEN2_CTRL 0x12 >> +#define TPS65917_REGEN3_CTRL 0x13 >> + >> static inline int palmas_read(struct palmas *palmas, unsigned int base, >> unsigned int reg, unsigned int *val) >> { -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index ccbb21f..52a24a9 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -30,6 +30,8 @@ #define PALMAS_CHIP_ID 0xC035 #define PALMAS_CHIP_CHARGER_ID 0xC036 +#define TPS65917_RESERVED -1 + #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ ((a) == PALMAS_CHIP_ID)) #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) @@ -184,6 +186,27 @@ enum palmas_regulators { PALMAS_NUM_REGS, }; +enum tps65917_regulators { + /* SMPS regulators */ + TPS65917_REG_SMPS1, + TPS65917_REG_SMPS2, + TPS65917_REG_SMPS3, + TPS65917_REG_SMPS4, + TPS65917_REG_SMPS5, + /* LDO regulators */ + TPS65917_REG_LDO1, + TPS65917_REG_LDO2, + TPS65917_REG_LDO3, + TPS65917_REG_LDO4, + TPS65917_REG_LDO5, + TPS65917_REG_REGEN1, + TPS65917_REG_REGEN2, + TPS65917_REG_REGEN3, + + /* Total number of regulators */ + TPS65917_NUM_REGS, +}; + /* External controll signal name */ enum { PALMAS_EXT_CONTROL_ENABLE1 = 0x1, @@ -228,6 +251,24 @@ enum palmas_external_requestor_id { PALMAS_EXTERNAL_REQSTR_ID_MAX, }; +enum tps65917_external_requestor_id { + TPS65917_EXTERNAL_REQSTR_ID_REGEN1, + TPS65917_EXTERNAL_REQSTR_ID_REGEN2, + TPS65917_EXTERNAL_REQSTR_ID_REGEN3, + TPS65917_EXTERNAL_REQSTR_ID_SMPS1, + TPS65917_EXTERNAL_REQSTR_ID_SMPS2, + TPS65917_EXTERNAL_REQSTR_ID_SMPS3, + TPS65917_EXTERNAL_REQSTR_ID_SMPS4, + TPS65917_EXTERNAL_REQSTR_ID_SMPS5, + TPS65917_EXTERNAL_REQSTR_ID_LDO1, + TPS65917_EXTERNAL_REQSTR_ID_LDO2, + TPS65917_EXTERNAL_REQSTR_ID_LDO3, + TPS65917_EXTERNAL_REQSTR_ID_LDO4, + TPS65917_EXTERNAL_REQSTR_ID_LDO5, + /* Last entry */ + TPS65917_EXTERNAL_REQSTR_ID_MAX, +}; + struct palmas_pmic_platform_data { /* An array of pointers to regulator init data indexed by regulator * ID @@ -349,6 +390,48 @@ struct palmas_gpadc_result { #define PALMAS_MAX_CHANNELS 16 +/* Define the tps65917 IRQ numbers */ +enum tps65917_irqs { + /* INT1 registers */ + TPS65917_RESERVED1, + TPS65917_PWRON_IRQ, + TPS65917_LONG_PRESS_KEY_IRQ, + TPS65917_RESERVED2, + TPS65917_PWRDOWN_IRQ, + TPS65917_HOTDIE_IRQ, + TPS65917_VSYS_MON_IRQ, + TPS65917_RESERVED3, + /* INT2 registers */ + TPS65917_RESERVED4, + TPS65917_OTP_ERROR_IRQ, + TPS65917_WDT_IRQ, + TPS65917_RESERVED5, + TPS65917_RESET_IN_IRQ, + TPS65917_FSD_IRQ, + TPS65917_SHORT_IRQ, + TPS65917_RESERVED6, + /* INT3 registers */ + TPS65917_GPADC_AUTO_0_IRQ, + TPS65917_GPADC_AUTO_1_IRQ, + TPS65917_GPADC_EOC_SW_IRQ, + TPS65917_RESREVED6, + TPS65917_RESERVED7, + TPS65917_RESERVED8, + TPS65917_RESERVED9, + TPS65917_VBUS_IRQ, + /* INT4 registers */ + TPS65917_GPIO_0_IRQ, + TPS65917_GPIO_1_IRQ, + TPS65917_GPIO_2_IRQ, + TPS65917_GPIO_3_IRQ, + TPS65917_GPIO_4_IRQ, + TPS65917_GPIO_5_IRQ, + TPS65917_GPIO_6_IRQ, + TPS65917_RESERVED10, + /* Total Number IRQs */ + TPS65917_NUM_IRQ, +}; + /* Define the palmas IRQ numbers */ enum palmas_irqs { /* INT1 registers */ @@ -400,6 +483,7 @@ struct palmas_pmic { int smps123; int smps457; + int smps12; int range[PALMAS_REG_SMPS10_OUT1]; unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; @@ -2871,6 +2955,715 @@ enum usb_irq_events { #define PALMAS_GPADC_TRIM15 0x0E #define PALMAS_GPADC_TRIM16 0x0F +/* TPS65917 Interrupt registers */ + +/* Registers for function INTERRUPT */ +#define TPS65917_INT1_STATUS 0x00 +#define TPS65917_INT1_MASK 0x01 +#define TPS65917_INT1_LINE_STATE 0x02 +#define TPS65917_INT2_STATUS 0x05 +#define TPS65917_INT2_MASK 0x06 +#define TPS65917_INT2_LINE_STATE 0x07 +#define TPS65917_INT3_STATUS 0x0A +#define TPS65917_INT3_MASK 0x0B +#define TPS65917_INT3_LINE_STATE 0x0C +#define TPS65917_INT4_STATUS 0x0F +#define TPS65917_INT4_MASK 0x10 +#define TPS65917_INT4_LINE_STATE 0x11 +#define TPS65917_INT4_EDGE_DETECT1 0x12 +#define TPS65917_INT4_EDGE_DETECT2 0x13 +#define TPS65917_INT_CTRL 0x14 + +/* Bit definitions for INT1_STATUS */ +#define TPS65917_INT1_STATUS_VSYS_MON 0x40 +#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_STATUS_HOTDIE 0x20 +#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_STATUS_PWRDOWN 0x10 +#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_STATUS_PWRON 0x02 +#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 + +/* Bit definitions for INT1_MASK */ +#define TPS65917_INT1_MASK_VSYS_MON 0x40 +#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_MASK_HOTDIE 0x20 +#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_MASK_PWRDOWN 0x10 +#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_MASK_PWRON 0x02 +#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 + +/* Bit definitions for INT1_LINE_STATE */ +#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 +#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 +#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 +#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 +#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 +#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 +#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 +#define TPS65917_INT1_LINE_STATE_PWRON 0x02 +#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 + +/* Bit definitions for INT2_STATUS */ +#define TPS65917_INT2_STATUS_SHORT 0x40 +#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 +#define TPS65917_INT2_STATUS_FSD 0x20 +#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 +#define TPS65917_INT2_STATUS_RESET_IN 0x10 +#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_STATUS_WDT 0x04 +#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 +#define TPS65917_INT2_STATUS_OTP_ERROR 0x02 +#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT2_MASK */ +#define TPS65917_INT2_MASK_SHORT 0x40 +#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 +#define TPS65917_INT2_MASK_FSD 0x20 +#define TPS65917_INT2_MASK_FSD_SHIFT 0x05 +#define TPS65917_INT2_MASK_RESET_IN 0x10 +#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_MASK_WDT 0x04 +#define TPS65917_INT2_MASK_WDT_SHIFT 0x02 +#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 +#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT2_LINE_STATE */ +#define TPS65917_INT2_LINE_STATE_SHORT 0x40 +#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 +#define TPS65917_INT2_LINE_STATE_FSD 0x20 +#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 +#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 +#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 +#define TPS65917_INT2_LINE_STATE_WDT 0x04 +#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 +#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 +#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 + +/* Bit definitions for INT3_STATUS */ +#define TPS65917_INT3_STATUS_VBUS 0x80 +#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 +#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT3_MASK */ +#define TPS65917_INT3_MASK_VBUS 0x80 +#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 +#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT3_LINE_STATE */ +#define TPS65917_INT3_LINE_STATE_VBUS 0x80 +#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 +#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 +#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 + +/* Bit definitions for INT4_STATUS */ +#define TPS65917_INT4_STATUS_GPIO_6 0x40 +#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_STATUS_GPIO_5 0x20 +#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_STATUS_GPIO_4 0x10 +#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_STATUS_GPIO_3 0x08 +#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_STATUS_GPIO_2 0x04 +#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_STATUS_GPIO_1 0x02 +#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_STATUS_GPIO_0 0x01 +#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_MASK */ +#define TPS65917_INT4_MASK_GPIO_6 0x40 +#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_MASK_GPIO_5 0x20 +#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_MASK_GPIO_4 0x10 +#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_MASK_GPIO_3 0x08 +#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_MASK_GPIO_2 0x04 +#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_MASK_GPIO_1 0x02 +#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_MASK_GPIO_0 0x01 +#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_LINE_STATE */ +#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 +#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 +#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 +#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 +#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 +#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 +#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 +#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 +#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 +#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 +#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 +#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 +#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 +#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 + +/* Bit definitions for INT4_EDGE_DETECT1 */ +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 +#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 + +/* Bit definitions for INT4_EDGE_DETECT2 */ +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 +#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 + +/* Bit definitions for INT_CTRL */ +#define TPS65917_INT_CTRL_INT_PENDING 0x04 +#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 +#define TPS65917_INT_CTRL_INT_CLEAR 0x01 +#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 + +/* TPS65917 SMPS Registers */ + +/* Registers for function SMPS */ +#define TPS65917_SMPS1_CTRL 0x00 +#define TPS65917_SMPS1_FORCE 0x02 +#define TPS65917_SMPS1_VOLTAGE 0x03 +#define TPS65917_SMPS2_CTRL 0x04 +#define TPS65917_SMPS2_FORCE 0x06 +#define TPS65917_SMPS2_VOLTAGE 0x07 +#define TPS65917_SMPS3_CTRL 0x0C +#define TPS65917_SMPS3_FORCE 0x0E +#define TPS65917_SMPS3_VOLTAGE 0x0F +#define TPS65917_SMPS4_CTRL 0x10 +#define TPS65917_SMPS4_VOLTAGE 0x13 +#define TPS65917_SMPS5_CTRL 0x18 +#define TPS65917_SMPS5_VOLTAGE 0x1B +#define TPS65917_SMPS_CTRL 0x24 +#define TPS65917_SMPS_PD_CTRL 0x25 +#define TPS65917_SMPS_THERMAL_EN 0x27 +#define TPS65917_SMPS_THERMAL_STATUS 0x28 +#define TPS65917_SMPS_SHORT_STATUS 0x29 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A +#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B +#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C + +/* Bit definitions for SMPS1_CTRL */ +#define TPS65917_SMPS1_CTRL_WR_S 0x80 +#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS1_FORCE */ +#define TPS65917_SMPS1_FORCE_CMD 0x80 +#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS1_VOLTAGE */ +#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS2_CTRL */ +#define TPS65917_SMPS2_CTRL_WR_S 0x80 +#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS2_FORCE */ +#define TPS65917_SMPS2_FORCE_CMD 0x80 +#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS2_VOLTAGE */ +#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS3_CTRL */ +#define TPS65917_SMPS3_CTRL_WR_S 0x80 +#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS3_FORCE */ +#define TPS65917_SMPS3_FORCE_CMD 0x80 +#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 +#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F +#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS3_VOLTAGE */ +#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS4_CTRL */ +#define TPS65917_SMPS4_CTRL_WR_S 0x80 +#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS4_VOLTAGE */ +#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS5_CTRL */ +#define TPS65917_SMPS5_CTRL_WR_S 0x80 +#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 +#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 +#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 +#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C +#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 +#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for SMPS5_VOLTAGE */ +#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 +#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 +#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F +#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for SMPS_CTRL */ +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 +#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 +#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 + +/* Bit definitions for SMPS_PD_CTRL */ +#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 +#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 +#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 +#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 +#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 +#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_THERMAL_EN */ +#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 +#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 +#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 +#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 + +/* Bit definitions for SMPS_THERMAL_STATUS */ +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 +#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 + +/* Bit definitions for SMPS_SHORT_STATUS */ +#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 +#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 +#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 +#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 +#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 +#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 +#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_POWERGOOD_MASK1 */ +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 +#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 + +/* Bit definitions for SMPS_POWERGOOD_MASK2 */ +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 +#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 +#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 + +/* Bit definitions for SMPS_PLL_CTRL */ + +#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 +#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 + +/* Registers for function LDO */ +#define TPS65917_LDO1_CTRL 0x00 +#define TPS65917_LDO1_VOLTAGE 0x01 +#define TPS65917_LDO2_CTRL 0x02 +#define TPS65917_LDO2_VOLTAGE 0x03 +#define TPS65917_LDO3_CTRL 0x04 +#define TPS65917_LDO3_VOLTAGE 0x05 +#define TPS65917_LDO4_CTRL 0x0E +#define TPS65917_LDO4_VOLTAGE 0x0F +#define TPS65917_LDO5_CTRL 0x12 +#define TPS65917_LDO5_VOLTAGE 0x13 +#define TPS65917_LDO_PD_CTRL1 0x1B +#define TPS65917_LDO_PD_CTRL2 0x1C +#define TPS65917_LDO_SHORT_STATUS1 0x1D +#define TPS65917_LDO_SHORT_STATUS2 0x1E +#define TPS65917_LDO_PD_CTRL3 0x2D +#define TPS65917_LDO_SHORT_STATUS3 0x2E + +/* Bit definitions for LDO1_CTRL */ +#define TPS65917_LDO1_CTRL_WR_S 0x80 +#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 +#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 +#define TPS65917_LDO1_CTRL_STATUS 0x10 +#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO1_VOLTAGE */ +#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO2_CTRL */ +#define TPS65917_LDO2_CTRL_WR_S 0x80 +#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 +#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 +#define TPS65917_LDO2_CTRL_STATUS 0x10 +#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO2_VOLTAGE */ +#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO3_CTRL */ +#define TPS65917_LDO3_CTRL_WR_S 0x80 +#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO3_CTRL_STATUS 0x10 +#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO3_VOLTAGE */ +#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO4_CTRL */ +#define TPS65917_LDO4_CTRL_WR_S 0x80 +#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO4_CTRL_STATUS 0x10 +#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO4_VOLTAGE */ +#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO5_CTRL */ +#define TPS65917_LDO5_CTRL_WR_S 0x80 +#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 +#define TPS65917_LDO5_CTRL_STATUS 0x10 +#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 +#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for LDO5_VOLTAGE */ +#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F +#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 + +/* Bit definitions for LDO_PD_CTRL1 */ +#define TPS65917_LDO_PD_CTRL1_LDO4 0x80 +#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 +#define TPS65917_LDO_PD_CTRL1_LDO2 0x02 +#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 +#define TPS65917_LDO_PD_CTRL1_LDO1 0x01 +#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 + +/* Bit definitions for LDO_PD_CTRL2 */ +#define TPS65917_LDO_PD_CTRL2_LDO3 0x04 +#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 +#define TPS65917_LDO_PD_CTRL2_LDO5 0x02 +#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 + +/* Bit definitions for LDO_PD_CTRL3 */ +#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 +#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 + +/* Bit definitions for LDO_SHORT_STATUS1 */ +#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 +#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 +#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 +#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 +#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 +#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 + +/* Bit definitions for LDO_SHORT_STATUS2 */ +#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 +#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 +#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 +#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 + +/* Bit definitions for LDO_SHORT_STATUS2 */ +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 +#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 + +/* Bit definitions for REGEN1_CTRL */ +#define TPS65917_REGEN1_CTRL_STATUS 0x10 +#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for PLLEN_CTRL */ +#define TPS65917_PLLEN_CTRL_STATUS 0x10 +#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 +#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for REGEN2_CTRL */ +#define TPS65917_REGEN2_CTRL_STATUS 0x10 +#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Bit definitions for NSLEEP_RES_ASSIGN */ +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 +#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_SMPS_ASSIGN */ +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for ENABLE1_RES_ASSIGN */ +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 +#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_SMPS_ASSIGN */ +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for ENABLE2_RES_ASSIGN */ +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 +#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 +#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_SMPS_ASSIGN */ +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 +#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 +#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 + +/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 +#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 + +/* Bit definitions for REGEN3_CTRL */ +#define TPS65917_REGEN3_CTRL_STATUS 0x10 +#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 +#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 +#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 +#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 + +/* Registers for function RESOURCE */ +#define TPS65917_REGEN1_CTRL 0x2 +#define TPS65917_PLLEN_CTRL 0x3 +#define TPS65917_NSLEEP_RES_ASSIGN 0x6 +#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 +#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 +#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 +#define TPS65917_ENABLE1_RES_ASSIGN 0xA +#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB +#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC +#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD +#define TPS65917_ENABLE2_RES_ASSIGN 0xE +#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF +#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 +#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 +#define TPS65917_REGEN2_CTRL 0x12 +#define TPS65917_REGEN3_CTRL 0x13 + static inline int palmas_read(struct palmas *palmas, unsigned int base, unsigned int reg, unsigned int *val) {
Add tps65917 specific definitions and enums. Signed-off-by: Keerthy <j-keerthy@ti.com> --- include/linux/mfd/palmas.h | 793 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 793 insertions(+)