| Message ID | 1402565920-5636-1-git-send-email-jszhang@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.
Hi Russell, On Thu, 12 Jun 2014 02:44:23 -0700 Russell King - ARM Linux <linux@arm.linux.org.uk> wrote: > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote: > > For all BG2Q SoCs, 2 cycles is the best/correct value > > It would be a good idea to set all these parameters if you need to set > them at all - in other words, setting arm,dirty-latency as well, as > that's all part of the timing specification. > Thanks for reviewing this patch. I will check with SoC people to find the correct dirty-latency value. Thanks, Jisheng
Hi Russell, On Thu, 12 Jun 2014 03:15:03 -0700 Jisheng Zhang <jszhang@marvell.com> wrote: > Hi Russell, > > On Thu, 12 Jun 2014 02:44:23 -0700 > Russell King - ARM Linux <linux@arm.linux.org.uk> wrote: > > > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote: > > > For all BG2Q SoCs, 2 cycles is the best/correct value > > > > It would be a good idea to set all these parameters if you need to set > > them at all - in other words, setting arm,dirty-latency as well, as > > that's all part of the timing specification. > > > > Thanks for reviewing this patch. I will check with SoC people to find the > correct dirty-latency value. The BG2Q L2 cache controller is PL310, so no "dirty-latency" Thanks, Jisheng
On 06/12/2014 11:38 AM, Jisheng Zhang wrote: > For all BG2Q SoCs, 2 cycles is the best/correct value > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Applied to berlin/dt with following fixed patch title: "ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles" Thanks! > --- > arch/arm/boot/dts/berlin2q.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi > index 635a16a..3f95dc5 100644 > --- a/arch/arm/boot/dts/berlin2q.dtsi > +++ b/arch/arm/boot/dts/berlin2q.dtsi > @@ -90,6 +90,8 @@ > compatible = "arm,pl310-cache"; > reg = <0xac0000 0x1000>; > cache-level = <2>; > + arm,data-latency = <2 2 2>; > + arm,tag-latency = <2 2 2>; > }; > > scu: snoop-control-unit@ad0000 { >
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 635a16a..3f95dc5 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -90,6 +90,8 @@ compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; }; scu: snoop-control-unit@ad0000 {
For all BG2Q SoCs, 2 cycles is the best/correct value Signed-off-by: Jisheng Zhang <jszhang@marvell.com> --- arch/arm/boot/dts/berlin2q.dtsi | 2 ++ 1 file changed, 2 insertions(+)