| Message ID | 5192928.MkINji4uKU@wuerfel (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/11/2014 09:35 AM, Arnd Bergmann wrote: > The OMAP4 camera support depends on I2C and VIDEO_V4L2, both > of which can be loadable modules. This causes build failures > if we want the camera driver to be built-in. > > This can be solved by turning the option into "tristate", > which unfortunately causes another problem, because the > driver incorrectly calls a platform-internal interface > for omap4_ctrl_pad_readl/omap4_ctrl_pad_writel. > To work around that, we can export those symbols, but > that isn't really the correct solution, as we should not > have dependencies on platform code this way. > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > This is one of just two patches we currently need to get > 'make allmodconfig' to build again on ARM. > > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c > index 751f354..05d2d98 100644 > --- a/arch/arm/mach-omap2/control.c > +++ b/arch/arm/mach-omap2/control.c > @@ -190,11 +190,13 @@ u32 omap4_ctrl_pad_readl(u16 offset) > { > return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); > } > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_readl); > > void omap4_ctrl_pad_writel(u32 val, u16 offset) > { > writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); > } > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_writel); > > #ifdef CONFIG_ARCH_OMAP3 > > diff --git a/drivers/staging/media/omap4iss/Kconfig b/drivers/staging/media/omap4iss/Kconfig > index 78b0fba..0c3e3c1 100644 > --- a/drivers/staging/media/omap4iss/Kconfig > +++ b/drivers/staging/media/omap4iss/Kconfig > @@ -1,5 +1,5 @@ > config VIDEO_OMAP4 > - bool "OMAP 4 Camera support" > + tristate "OMAP 4 Camera support" > depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && I2C && ARCH_OMAP4 > select VIDEOBUF2_DMA_CONTIG > ---help--- > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > This was discussed in detail here: http://marc.info/?t=140198692500001&r=1&w=2 Direct dependency from a staging driver to mach-omap2 driver is not something we'd like, right?
* Arnd Bergmann <arnd@arndb.de> [140611 07:37]: > The OMAP4 camera support depends on I2C and VIDEO_V4L2, both > of which can be loadable modules. This causes build failures > if we want the camera driver to be built-in. That's good news, but let's not fix it this way. > This can be solved by turning the option into "tristate", > which unfortunately causes another problem, because the > driver incorrectly calls a platform-internal interface > for omap4_ctrl_pad_readl/omap4_ctrl_pad_writel. > To work around that, we can export those symbols, but > that isn't really the correct solution, as we should not > have dependencies on platform code this way. > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > This is one of just two patches we currently need to get > 'make allmodconfig' to build again on ARM. > > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c > index 751f354..05d2d98 100644 > --- a/arch/arm/mach-omap2/control.c > +++ b/arch/arm/mach-omap2/control.c > @@ -190,11 +190,13 @@ u32 omap4_ctrl_pad_readl(u16 offset) > { > return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); > } > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_readl); > > void omap4_ctrl_pad_writel(u32 val, u16 offset) > { > writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); > } > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_writel); > > #ifdef CONFIG_ARCH_OMAP3 Exporting these will likely cause immediate misuse in other drivers all over the place. These should just use either pinctrl-single.c instead for muxing. Or if they are not mux registers, we do have the syscon mapping available in omap4.dtsi that pbias-regulator.c is already using. Laurent, got any better ideas? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony, On Wednesday 11 June 2014 07:47:54 Tony Lindgren wrote: > * Arnd Bergmann <arnd@arndb.de> [140611 07:37]: > > The OMAP4 camera support depends on I2C and VIDEO_V4L2, both > > of which can be loadable modules. This causes build failures > > if we want the camera driver to be built-in. > > That's good news, but let's not fix it this way. > > > This can be solved by turning the option into "tristate", > > which unfortunately causes another problem, because the > > driver incorrectly calls a platform-internal interface > > for omap4_ctrl_pad_readl/omap4_ctrl_pad_writel. > > To work around that, we can export those symbols, but > > that isn't really the correct solution, as we should not > > have dependencies on platform code this way. > > > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > > --- > > This is one of just two patches we currently need to get > > 'make allmodconfig' to build again on ARM. > > > > diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c > > index 751f354..05d2d98 100644 > > --- a/arch/arm/mach-omap2/control.c > > +++ b/arch/arm/mach-omap2/control.c > > @@ -190,11 +190,13 @@ u32 omap4_ctrl_pad_readl(u16 offset) > > { > > return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); > > } > > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_readl); > > > > void omap4_ctrl_pad_writel(u32 val, u16 offset) > > { > > writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); > > } > > +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_writel); > > > > #ifdef CONFIG_ARCH_OMAP3 > > Exporting these will likely cause immediate misuse in other > drivers all over the place. > > These should just use either pinctrl-single.c instead for muxing. > Or if they are not mux registers, we do have the syscon mapping > available in omap4.dtsi that pbias-regulator.c is already using. > > Laurent, got any better ideas? The ISS driver needs to write a single register, which contains several independent fields. They thus need to be controlled by a single driver. Some of them might be considered to be related to pinmuxing (although I disagree on that), others are certainly not about muxing (there are clock gate bits for instance). Using the syscon mapping seems like the best option. I'll give it a try.
* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 07:52]: > On Wednesday 11 June 2014 07:47:54 Tony Lindgren wrote: > > > > These should just use either pinctrl-single.c instead for muxing. > > Or if they are not mux registers, we do have the syscon mapping > > available in omap4.dtsi that pbias-regulator.c is already using. > > > > Laurent, got any better ideas? > > The ISS driver needs to write a single register, which contains several > independent fields. They thus need to be controlled by a single driver. Some > of them might be considered to be related to pinmuxing (although I disagree on > that), others are certainly not about muxing (there are clock gate bits for > instance). > > Using the syscon mapping seems like the best option. I'll give it a try. OK if it's not strictly pinctrl related then let's not use pinctrl-single,bits for it. You may be able to implement one or more framework drivers for it for pinctrl/regulator/clock/transceiver whatever that register is doing. In any case it's best to have that handling in a separate helper driver somewhere as it's a separate piece of hardware from the camera module. If it does not fit into any existing frameworks then it's best to have it in a separate driver with the camera driver. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony, On Thursday 12 June 2014 08:15:35 Tony Lindgren wrote: > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 07:52]: > > On Wednesday 11 June 2014 07:47:54 Tony Lindgren wrote: > > > These should just use either pinctrl-single.c instead for muxing. > > > Or if they are not mux registers, we do have the syscon mapping > > > available in omap4.dtsi that pbias-regulator.c is already using. > > > > > > Laurent, got any better ideas? > > > > The ISS driver needs to write a single register, which contains several > > independent fields. They thus need to be controlled by a single driver. > > Some of them might be considered to be related to pinmuxing (although I > > disagree on that), others are certainly not about muxing (there are clock > > gate bits for instance). > > > > Using the syscon mapping seems like the best option. I'll give it a try. > > OK if it's not strictly pinctrl related then let's not use > pinctrl-single,bits for it. You may be able to implement one or more > framework drivers for it for pinctrl/regulator/clock/transceiver > whatever that register is doing. > > In any case it's best to have that handling in a separate helper driver > somewhere as it's a separate piece of hardware from the camera module. > If it does not fit into any existing frameworks then it's best to have > it in a separate driver with the camera driver. The register contains the following fields that control the two CSI2 PHYs (PHY1 and PHY2). 31 CAMERARX_CSI22_LANEENABLE2 PHY2 Lane 2 (CSI22_DX2, CSI22_DY2) Enable 30 CAMERARX_CSI22_LANEENABLE1 PHY2 Lane 1 (CSI22_DX1, CSI22_DY1) Enable 29 CAMERARX_CSI22_LANEENABLE0 PHY2 Lane 0 (CSI22_DX0, CSI22_DY0) Enable 28 CAMERARX_CSI21_LANEENABLE4 PHY1 Lane 4 (CSI21_DX4, CSI21_DY4) Enable 27 CAMERARX_CSI21_LANEENABLE3 PHY1 Lane 3 (CSI21_DX3, CSI21_DY3) Enable 26 CAMERARX_CSI21_LANEENABLE2 PHY1 Lane 2 (CSI21_DX2, CSI21_DY2) Enable 25 CAMERARX_CSI21_LANEENABLE1 PHY1 Lane 1 (CSI21_DX1, CSI21_DY1) Enable 24 CAMERARX_CSI21_LANEENABLE0 PHY1 Lane 0 (CSI21_DX0, CSI21_DY0) Enable 21 CAMERARX_CSI22_CTRLCLKEN PHY2 Clock Enable 20:19 CAMERARX_CSI22_CAMMODE PHY2 Mode (CCP2, CSI1, CSI2) 18 CAMERARX_CSI21_CTRLCLKEN PHY1 Clock Enable 17:16 CAMERARX_CSI21_CAMMODE PHY1 Mode (CCP2, CSI1, CSI2) Bits 18 and 21 could be exposed through CCF. Bits 24 to 31 enable/disable the CSI2 lanes, so it could be argued that they could be exposed through the pinctrl framework. However, they need to be configured independently, possibly at runtime. I'm thus not sure pinctrl would be a good idea. Bits 17:16 and 20:19 don't fit in existing frameworks. Given that this register is specific to the ISS, I think handling it as a separate device through a separate driver would only complicate the implementation without any real benefit.
* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 08:32]: > Hi Tony, > > On Thursday 12 June 2014 08:15:35 Tony Lindgren wrote: > > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 07:52]: > > > On Wednesday 11 June 2014 07:47:54 Tony Lindgren wrote: > > > > These should just use either pinctrl-single.c instead for muxing. > > > > Or if they are not mux registers, we do have the syscon mapping > > > > available in omap4.dtsi that pbias-regulator.c is already using. > > > > > > > > Laurent, got any better ideas? > > > > > > The ISS driver needs to write a single register, which contains several > > > independent fields. They thus need to be controlled by a single driver. > > > Some of them might be considered to be related to pinmuxing (although I > > > disagree on that), others are certainly not about muxing (there are clock > > > gate bits for instance). > > > > > > Using the syscon mapping seems like the best option. I'll give it a try. > > > > OK if it's not strictly pinctrl related then let's not use > > pinctrl-single,bits for it. You may be able to implement one or more > > framework drivers for it for pinctrl/regulator/clock/transceiver > > whatever that register is doing. > > > > In any case it's best to have that handling in a separate helper driver > > somewhere as it's a separate piece of hardware from the camera module. > > If it does not fit into any existing frameworks then it's best to have > > it in a separate driver with the camera driver. > > The register contains the following fields that control the two CSI2 PHYs > (PHY1 and PHY2). > > 31 CAMERARX_CSI22_LANEENABLE2 PHY2 Lane 2 (CSI22_DX2, CSI22_DY2) Enable > 30 CAMERARX_CSI22_LANEENABLE1 PHY2 Lane 1 (CSI22_DX1, CSI22_DY1) Enable > 29 CAMERARX_CSI22_LANEENABLE0 PHY2 Lane 0 (CSI22_DX0, CSI22_DY0) Enable > 28 CAMERARX_CSI21_LANEENABLE4 PHY1 Lane 4 (CSI21_DX4, CSI21_DY4) Enable > 27 CAMERARX_CSI21_LANEENABLE3 PHY1 Lane 3 (CSI21_DX3, CSI21_DY3) Enable > 26 CAMERARX_CSI21_LANEENABLE2 PHY1 Lane 2 (CSI21_DX2, CSI21_DY2) Enable > 25 CAMERARX_CSI21_LANEENABLE1 PHY1 Lane 1 (CSI21_DX1, CSI21_DY1) Enable > 24 CAMERARX_CSI21_LANEENABLE0 PHY1 Lane 0 (CSI21_DX0, CSI21_DY0) Enable > 21 CAMERARX_CSI22_CTRLCLKEN PHY2 Clock Enable > 20:19 CAMERARX_CSI22_CAMMODE PHY2 Mode (CCP2, CSI1, CSI2) > 18 CAMERARX_CSI21_CTRLCLKEN PHY1 Clock Enable > 17:16 CAMERARX_CSI21_CAMMODE PHY1 Mode (CCP2, CSI1, CSI2) > > Bits 18 and 21 could be exposed through CCF. Bits 24 to 31 enable/disable the > CSI2 lanes, so it could be argued that they could be exposed through the > pinctrl framework. However, they need to be configured independently, possibly > at runtime. I'm thus not sure pinctrl would be a good idea. Bits 17:16 and > 20:19 don't fit in existing frameworks. OK thanks for the info. Sounds like drivers/phy might be the right location for it then and then the phy driver can use the syscon regmap. > Given that this register is specific to the ISS, I think handling it as a > separate device through a separate driver would only complicate the > implementation without any real benefit. Even though it's one register, it shoud still be treated separately from the camera driver. The problems with keeping the register access to the control module in the camera driver are at least following: 1. They live in separate hardware modules that can be clocked separately 2. Doing a read-back to flush a posted write in one hardware module most likely won't flush the write to other and that can lead into hard to find mysterious bugs 3. If we ever have a common system control module driver, we need to rewrite all the system control module register tinkering in the drivers So it's best to try to use an existing framework for it. That avoids tons of pain later on ;) Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony, On Thursday 12 June 2014 22:30:44 Tony Lindgren wrote: > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 08:32]: > > On Thursday 12 June 2014 08:15:35 Tony Lindgren wrote: > >> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 07:52]: > >>> On Wednesday 11 June 2014 07:47:54 Tony Lindgren wrote: > >>>> These should just use either pinctrl-single.c instead for muxing. > >>>> Or if they are not mux registers, we do have the syscon mapping > >>>> available in omap4.dtsi that pbias-regulator.c is already using. > >>>> > >>>> Laurent, got any better ideas? > >>> > >>> The ISS driver needs to write a single register, which contains > >>> several independent fields. They thus need to be controlled by a > >>> single driver. Some of them might be considered to be related to > >>> pinmuxing (although I disagree on that), others are certainly not > >>> about muxing (there are clock gate bits for instance). > >>> > >>> Using the syscon mapping seems like the best option. I'll give it a > >>> try. > >> > >> OK if it's not strictly pinctrl related then let's not use > >> pinctrl-single,bits for it. You may be able to implement one or more > >> framework drivers for it for pinctrl/regulator/clock/transceiver > >> whatever that register is doing. > >> > >> In any case it's best to have that handling in a separate helper driver > >> somewhere as it's a separate piece of hardware from the camera module. > >> If it does not fit into any existing frameworks then it's best to have > >> it in a separate driver with the camera driver. > > > > The register contains the following fields that control the two CSI2 PHYs > > (PHY1 and PHY2). > > > > 31 CAMERARX_CSI22_LANEENABLE2 PHY2 Lane 2 (CSI22_DX2, CSI22_DY2) > > Enable > > 30 CAMERARX_CSI22_LANEENABLE1 PHY2 Lane 1 (CSI22_DX1, CSI22_DY1) > > Enable > > 29 CAMERARX_CSI22_LANEENABLE0 PHY2 Lane 0 (CSI22_DX0, CSI22_DY0) > > Enable > > 28 CAMERARX_CSI21_LANEENABLE4 PHY1 Lane 4 (CSI21_DX4, CSI21_DY4) > > Enable > > 27 CAMERARX_CSI21_LANEENABLE3 PHY1 Lane 3 (CSI21_DX3, CSI21_DY3) > > Enable > > 26 CAMERARX_CSI21_LANEENABLE2 PHY1 Lane 2 (CSI21_DX2, CSI21_DY2) > > Enable > > 25 CAMERARX_CSI21_LANEENABLE1 PHY1 Lane 1 (CSI21_DX1, CSI21_DY1) > > Enable > > 24 CAMERARX_CSI21_LANEENABLE0 PHY1 Lane 0 (CSI21_DX0, CSI21_DY0) > > Enable > > 21 CAMERARX_CSI22_CTRLCLKEN PHY2 Clock Enable > > 20:19 CAMERARX_CSI22_CAMMODE PHY2 Mode (CCP2, CSI1, CSI2) > > 18 CAMERARX_CSI21_CTRLCLKEN PHY1 Clock Enable > > 17:16 CAMERARX_CSI21_CAMMODE PHY1 Mode (CCP2, CSI1, CSI2) > > > > Bits 18 and 21 could be exposed through CCF. Bits 24 to 31 enable/disable > > the CSI2 lanes, so it could be argued that they could be exposed through > > the pinctrl framework. However, they need to be configured independently, > > possibly at runtime. I'm thus not sure pinctrl would be a good idea. Bits > > 17:16 and 20:19 don't fit in existing frameworks. > > OK thanks for the info. Sounds like drivers/phy might be the right location > for it then and then the phy driver can use the syscon regmap. > > > Given that this register is specific to the ISS, I think handling it as a > > separate device through a separate driver would only complicate the > > implementation without any real benefit. > > Even though it's one register, it shoud still be treated separately from > the camera driver. The problems with keeping the register access to the > control module in the camera driver are at least following: > > 1. They live in separate hardware modules that can be clocked separately Actually I don't think that's true. The CSI2 PHY is part of the camera device, with all its registers but the one above in the camera device register space. For some weird reason a couple of bits were pushed to the control module, but that doesn't make the CSI2 PHY itself a separate device. > 2. Doing a read-back to flush a posted write in one hardware module most > likely won't flush the write to other and that can lead into hard to > find mysterious bugs The OMAP4 ISS driver can just read back the CAMERA_RX register, can't it ? > 3. If we ever have a common system control module driver, we need to > rewrite all the system control module register tinkering in the drivers Sure, but that's already the case today, as the OMAP4 ISS driver already accesses the control module register directly. I won't make that worse :-) > So it's best to try to use an existing framework for it. That avoids tons of > pain later on ;) I agree, but I don't think the PHY framework would be the right abstraction. As explained above the CSI2 PHY is part of the OMAP4 ISS, so modeling its single control module register as a PHY would be a hack.
* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 23:48]: > On Thursday 12 June 2014 22:30:44 Tony Lindgren wrote: > > > > 1. They live in separate hardware modules that can be clocked separately > > Actually I don't think that's true. The CSI2 PHY is part of the camera device, > with all its registers but the one above in the camera device register space. > For some weird reason a couple of bits were pushed to the control module, but > that doesn't make the CSI2 PHY itself a separate device. Yes they are separate. Anything in the system control module is a separate hardware module from the other devices. So in this case the CSI2 PHY is part of the system control module, not the camera module. > > 2. Doing a read-back to flush a posted write in one hardware module most > > likely won't flush the write to other and that can lead into hard to > > find mysterious bugs > > The OMAP4 ISS driver can just read back the CAMERA_RX register, can't it ? Right, but you would have to do readbacks both from the phy register and camera register to ensure writes get written. It's best to keep the logic completely separate especially considering that they can be clocked separately. > > 3. If we ever have a common system control module driver, we need to > > rewrite all the system control module register tinkering in the drivers > > Sure, but that's already the case today, as the OMAP4 ISS driver already > accesses the control module register directly. I won't make that worse :-) Well it's in staging for a reason :) > > So it's best to try to use an existing framework for it. That avoids tons of > > pain later on ;) > > I agree, but I don't think the PHY framework would be the right abstraction. > As explained above the CSI2 PHY is part of the OMAP4 ISS, so modeling its > single control module register as a PHY would be a hack. Well that register belongs to the system control module, not the camera module. It's not like the camera IO space is out of registers or something! :) We're already handling similar control module phy cases, see for example drivers/phy/phy-omap-control.c. Maybe you have most of the code already there? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony, On Friday 13 June 2014 00:53:25 Tony Lindgren wrote: > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 23:48]: > > On Thursday 12 June 2014 22:30:44 Tony Lindgren wrote: > > > 1. They live in separate hardware modules that can be clocked separately > > > > Actually I don't think that's true. The CSI2 PHY is part of the camera > > device, with all its registers but the one above in the camera device > > register space. For some weird reason a couple of bits were pushed to the > > control module, but that doesn't make the CSI2 PHY itself a separate > > device. > > Yes they are separate. Anything in the system control module is > a separate hardware module from the other devices. So in this case > the CSI2 PHY is part of the system control module, not the camera > module. Section 8.2.3 ("ISS CSI2 PHY") of the OMAP4460 TRM (revision AA) documents the CSI2 PHY is being part of the ISS, with three PHY registers in the ISS register space (not counting the PHY interrupt and status bits in several other ISS registers) and one register in the system control module register space. It's far from clear which power domain(s) is (are) involved. > > > 2. Doing a read-back to flush a posted write in one hardware module most > > > likely won't flush the write to other and that can lead into hard to > > > find mysterious bugs > > > > The OMAP4 ISS driver can just read back the CAMERA_RX register, can't it ? > > Right, but you would have to do readbacks both from the phy register and > camera register to ensure writes get written. It's best to keep the > logic completely separate especially considering that they can be > clocked separately. > > > > 3. If we ever have a common system control module driver, we need to > > > rewrite all the system control module register tinkering in the > > > drivers > > > > Sure, but that's already the case today, as the OMAP4 ISS driver already > > accesses the control module register directly. I won't make that worse :-) > > Well it's in staging for a reason :) > > > > So it's best to try to use an existing framework for it. That avoids > > > tons of pain later on ;) > > > > I agree, but I don't think the PHY framework would be the right > > abstraction. As explained above the CSI2 PHY is part of the OMAP4 ISS, so > > modeling its single control module register as a PHY would be a hack. > > Well that register belongs to the system control module, not the > camera module. It's not like the camera IO space is out of registers > or something! :) The PHY has 3 registers in the ISS I/O space and one register in the control module I/O space. I have no idea why they've split it that way. The clock enable bits are especially "interested", the source clock (CAM_PHY_CTRL_FCLK) comes from the ISS as documented in section 8.1.1 ("ISS Integration"), is gated by the control module (the gated clock is called CTRLCLK) and then goes back to the ISS CSI2 PHY (it's mentioned in the CSI2 PHY "REGISTER1" documentation). > We're already handling similar control module phy cases, see for > example drivers/phy/phy-omap-control.c. Maybe you have most of the > code already there? I'm afraid not. For PHYs that are in the system control module that solution is perfectly fine, but the CSI2 PHY isn't (or at least not all of it). I would be fine with writing a separate PHY driver if the PHY was completely separate. As the documentation doesn't make it clear which part of the hardware belongs to which module, matching the software implementation with an unknown hardware implementation would be pretty difficult :-) If you have a couple of minutes to spare and can look at the CSI2 PHY documentation in the TRM, you might be more successful than me figuring out how the hardware is implemented.
* Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140613 03:30]: > Hi Tony, > > On Friday 13 June 2014 00:53:25 Tony Lindgren wrote: > > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 23:48]: > > > On Thursday 12 June 2014 22:30:44 Tony Lindgren wrote: > > > > 1. They live in separate hardware modules that can be clocked separately > > > > > > Actually I don't think that's true. The CSI2 PHY is part of the camera > > > device, with all its registers but the one above in the camera device > > > register space. For some weird reason a couple of bits were pushed to the > > > control module, but that doesn't make the CSI2 PHY itself a separate > > > device. > > > > Yes they are separate. Anything in the system control module is > > a separate hardware module from the other devices. So in this case > > the CSI2 PHY is part of the system control module, not the camera > > module. > > Section 8.2.3 ("ISS CSI2 PHY") of the OMAP4460 TRM (revision AA) documents the > CSI2 PHY is being part of the ISS, with three PHY registers in the ISS > register space (not counting the PHY interrupt and status bits in several > other ISS registers) and one register in the system control module register > space. It's far from clear which power domain(s) is (are) involved. OK I see. The register in the system control module just contains some pin and clock related resources for the phy. > > > > 2. Doing a read-back to flush a posted write in one hardware module most > > > > likely won't flush the write to other and that can lead into hard to > > > > find mysterious bugs > > > > > > The OMAP4 ISS driver can just read back the CAMERA_RX register, can't it ? > > > > Right, but you would have to do readbacks both from the phy register and > > camera register to ensure writes get written. It's best to keep the > > logic completely separate especially considering that they can be > > clocked separately. > > > > > > 3. If we ever have a common system control module driver, we need to > > > > rewrite all the system control module register tinkering in the > > > > drivers > > > > > > Sure, but that's already the case today, as the OMAP4 ISS driver already > > > accesses the control module register directly. I won't make that worse :-) > > > > Well it's in staging for a reason :) > > > > > > So it's best to try to use an existing framework for it. That avoids > > > > tons of pain later on ;) > > > > > > I agree, but I don't think the PHY framework would be the right > > > abstraction. As explained above the CSI2 PHY is part of the OMAP4 ISS, so > > > modeling its single control module register as a PHY would be a hack. > > > > Well that register belongs to the system control module, not the > > camera module. It's not like the camera IO space is out of registers > > or something! :) > > The PHY has 3 registers in the ISS I/O space and one register in the control > module I/O space. I have no idea why they've split it that way. The clock > enable bits are especially "interested", the source clock (CAM_PHY_CTRL_FCLK) > comes from the ISS as documented in section 8.1.1 ("ISS Integration"), is > gated by the control module (the gated clock is called CTRLCLK) and then goes > back to the ISS CSI2 PHY (it's mentioned in the CSI2 PHY "REGISTER1" > documentation). > > > We're already handling similar control module phy cases, see for > > example drivers/phy/phy-omap-control.c. Maybe you have most of the > > code already there? > > I'm afraid not. For PHYs that are in the system control module that solution > is perfectly fine, but the CSI2 PHY isn't (or at least not all of it). > > I would be fine with writing a separate PHY driver if the PHY was completely > separate. As the documentation doesn't make it clear which part of the > hardware belongs to which module, matching the software implementation with an > unknown hardware implementation would be pretty difficult :-) Yeah it seems the phy driver would still have to use the pin resources in the system control module. > If you have a couple of minutes to spare and can look at the CSI2 PHY > documentation in the TRM, you might be more successful than me figuring out > how the hardware is implemented. Took a look and it seems the phy is split into two parts. So probably using the syscon mapping for the register in scm are is a good start. At least then there's some protection from drivers tinkering directly with the system control modules. Maybe s ee what drivers/regulator/pbias-regulator.c is doing with syscon to see if that works? Moving that to some phy driver later on should be trivial if needed :) Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony, On Friday 13 June 2014 04:10:12 Tony Lindgren wrote: > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140613 03:30]: > > On Friday 13 June 2014 00:53:25 Tony Lindgren wrote: > > > * Laurent Pinchart <laurent.pinchart@ideasonboard.com> [140612 23:48]: > > > > On Thursday 12 June 2014 22:30:44 Tony Lindgren wrote: > > > > > 1. They live in separate hardware modules that can be clocked > > > > > separately > > > > > > > > Actually I don't think that's true. The CSI2 PHY is part of the camera > > > > device, with all its registers but the one above in the camera device > > > > register space. For some weird reason a couple of bits were pushed to > > > > the control module, but that doesn't make the CSI2 PHY itself a > > > > separate device. > > > > > > Yes they are separate. Anything in the system control module is > > > a separate hardware module from the other devices. So in this case > > > the CSI2 PHY is part of the system control module, not the camera > > > module. > > > > Section 8.2.3 ("ISS CSI2 PHY") of the OMAP4460 TRM (revision AA) documents > > the CSI2 PHY is being part of the ISS, with three PHY registers in the > > ISS register space (not counting the PHY interrupt and status bits in > > several other ISS registers) and one register in the system control > > module register space. It's far from clear which power domain(s) is (are) > > involved. > > OK I see. The register in the system control module just contains some > pin and clock related resources for the phy. And the configuration of the PHY mode (CCP2, CSI1 or CSI2). It really seems like random bits :-) > > > > > 2. Doing a read-back to flush a posted write in one hardware module > > > > > most likely won't flush the write to other and that can lead into > > > > > hard to find mysterious bugs > > > > > > > > The OMAP4 ISS driver can just read back the CAMERA_RX register, can't > > > > it ? > > > > > > Right, but you would have to do readbacks both from the phy register and > > > camera register to ensure writes get written. It's best to keep the > > > logic completely separate especially considering that they can be > > > clocked separately. > > > > > > > > 3. If we ever have a common system control module driver, we need to > > > > > rewrite all the system control module register tinkering in the > > > > > drivers > > > > > > > > Sure, but that's already the case today, as the OMAP4 ISS driver > > > > already accesses the control module register directly. I won't make > > > > that worse :-) > > > > > > Well it's in staging for a reason :) > > > > > > > > So it's best to try to use an existing framework for it. That avoids > > > > > tons of pain later on ;) > > > > > > > > I agree, but I don't think the PHY framework would be the right > > > > abstraction. As explained above the CSI2 PHY is part of the OMAP4 ISS, > > > > so modeling its single control module register as a PHY would be a > > > > hack. > > > > > > Well that register belongs to the system control module, not the > > > camera module. It's not like the camera IO space is out of registers > > > or something! :) > > > > The PHY has 3 registers in the ISS I/O space and one register in the > > control module I/O space. I have no idea why they've split it that way. > > The clock enable bits are especially "interested", the source clock > > (CAM_PHY_CTRL_FCLK) comes from the ISS as documented in section 8.1.1 > > ("ISS Integration"), is gated by the control module (the gated clock is > > called CTRLCLK) and then goes back to the ISS CSI2 PHY (it's mentioned in > > the CSI2 PHY "REGISTER1" documentation). > > > > > We're already handling similar control module phy cases, see for > > > example drivers/phy/phy-omap-control.c. Maybe you have most of the > > > code already there? > > > > I'm afraid not. For PHYs that are in the system control module that > > solution is perfectly fine, but the CSI2 PHY isn't (or at least not all > > of it). > > > > I would be fine with writing a separate PHY driver if the PHY was > > completely separate. As the documentation doesn't make it clear which > > part of the hardware belongs to which module, matching the software > > implementation with an unknown hardware implementation would be pretty > > difficult :-) > > Yeah it seems the phy driver would still have to use the pin resources > in the system control module. > > > If you have a couple of minutes to spare and can look at the CSI2 PHY > > documentation in the TRM, you might be more successful than me figuring > > out how the hardware is implemented. > > Took a look and it seems the phy is split into two parts. So probably > using the syscon mapping for the register in scm are is a good start. > At least then there's some protection from drivers tinkering directly > with the system control modules. That's my plan. > Maybe s ee what drivers/regulator/pbias-regulator.c is doing with > syscon to see if that works? Moving that to some phy driver later on > should be trivial if needed :) I'll have a look, but I'm not sure whether the same approach will be possible.
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 751f354..05d2d98 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -190,11 +190,13 @@ u32 omap4_ctrl_pad_readl(u16 offset) { return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); } +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_readl); void omap4_ctrl_pad_writel(u32 val, u16 offset) { writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); } +EXPORT_SYMBOL_GPL(omap4_ctrl_pad_writel); #ifdef CONFIG_ARCH_OMAP3 diff --git a/drivers/staging/media/omap4iss/Kconfig b/drivers/staging/media/omap4iss/Kconfig index 78b0fba..0c3e3c1 100644 --- a/drivers/staging/media/omap4iss/Kconfig +++ b/drivers/staging/media/omap4iss/Kconfig @@ -1,5 +1,5 @@ config VIDEO_OMAP4 - bool "OMAP 4 Camera support" + tristate "OMAP 4 Camera support" depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && I2C && ARCH_OMAP4 select VIDEOBUF2_DMA_CONTIG ---help---
The OMAP4 camera support depends on I2C and VIDEO_V4L2, both of which can be loadable modules. This causes build failures if we want the camera driver to be built-in. This can be solved by turning the option into "tristate", which unfortunately causes another problem, because the driver incorrectly calls a platform-internal interface for omap4_ctrl_pad_readl/omap4_ctrl_pad_writel. To work around that, we can export those symbols, but that isn't really the correct solution, as we should not have dependencies on platform code this way. Signed-off-by: Arnd Bergmann <arnd@arndb.de> --- This is one of just two patches we currently need to get 'make allmodconfig' to build again on ARM. -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html