| Message ID | 1401345500-20188-8-git-send-email-kishon@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: > From: Keerthy <j-keerthy@ti.com> > > Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck > from dpll_pcie_ref_ck. Why? Needs a better changelog also. -Tero > > Cc: Rajendra Nayak <rnayak@ti.com> > Cc: Tero Kristo <t-kristo@ti.com> > Cc: Paul Walmsley <paul@pwsan.com> > Signed-off-by: Keerthy <j-keerthy@ti.com> > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi > index 55e95c5..44993ec 100644 > --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi > +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi > @@ -1152,7 +1152,7 @@ > > apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { > compatible = "ti,mux-clock"; > - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; > + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; > #clock-cells = <0>; > reg = <0x021c 0x4>; > ti,bit-shift = <7>; > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tero, On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote: > On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >> From: Keerthy <j-keerthy@ti.com> >> >> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck >> from dpll_pcie_ref_ck. > > Why? Needs a better changelog also. Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM shows the signal name for the output of post divider (M2) is CLKOUTLDO. Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as input to apll mux. So the actual output of dpll should be dpll_pcie_ref_m2ldo_ck instead of dpll_pcie_ref_ck (which is the input of apll mux). Thanks Kishon > > -Tero > >> >> Cc: Rajendra Nayak <rnayak@ti.com> >> Cc: Tero Kristo <t-kristo@ti.com> >> Cc: Paul Walmsley <paul@pwsan.com> >> Signed-off-by: Keerthy <j-keerthy@ti.com> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 55e95c5..44993ec 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -1152,7 +1152,7 @@ >> >> apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { >> compatible = "ti,mux-clock"; >> - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; >> + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; >> #clock-cells = <0>; >> reg = <0x021c 0x4>; >> ti,bit-shift = <7>; >> > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/19/2014 04:00 PM, Kishon Vijay Abraham I wrote: > Hi Tero, > > On Thursday 19 June 2014 04:42 PM, Tero Kristo wrote: >> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >>> From: Keerthy <j-keerthy@ti.com> >>> >>> Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck >>> from dpll_pcie_ref_ck. >> >> Why? Needs a better changelog also. > > Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM > shows the signal name for the output of post divider (M2) is CLKOUTLDO. > > Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as > input to apll mux. > > So the actual output of dpll should be dpll_pcie_ref_m2ldo_ck instead of > dpll_pcie_ref_ck (which is the input of apll mux). Yep, this is what I want to see in the changelog, so please repost. The original changelog had no info on it whatsoever. -Tero > > Thanks > Kishon >> >> -Tero >> >>> >>> Cc: Rajendra Nayak <rnayak@ti.com> >>> Cc: Tero Kristo <t-kristo@ti.com> >>> Cc: Paul Walmsley <paul@pwsan.com> >>> Signed-off-by: Keerthy <j-keerthy@ti.com> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>> --- >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> index 55e95c5..44993ec 100644 >>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> @@ -1152,7 +1152,7 @@ >>> >>> apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { >>> compatible = "ti,mux-clock"; >>> - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; >>> + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; >>> #clock-cells = <0>; >>> reg = <0x021c 0x4>; >>> ti,bit-shift = <7>; >>> >> -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 55e95c5..44993ec 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1152,7 +1152,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { compatible = "ti,mux-clock"; - clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>; #clock-cells = <0>; reg = <0x021c 0x4>; ti,bit-shift = <7>;